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Unclamped inductive stressing of GaN and SiC Cascode power devices to failure at elevated temperatures
Ist Teil von
Microelectronics and reliability, 2022-11, Vol.138, p.114711, Article 114711
Ort / Verlag
Elsevier Ltd
Erscheinungsjahr
2022
Link zum Volltext
Quelle
ScienceDirect Journals (5 years ago - present)
Beschreibungen/Notizen
In this paper, the ruggedness performance of GaN HEMT and SiC JFET devices in cascode configuration with a low voltage silicon power MOSFET has been evaluated experimentally. The impact of the bus voltage on the drain current and avalanche energy are investigated as well as the temperature sweep to enable analysis of the alternation of these parameters on the Unclamped Inductive Switching (UIS) ruggedness of cascode devices. The experimental measurements show that the GaN cascode devices have lower avalanche energy rating when compared with the closely rated SiC cascode devices just before the failure. SiC cascode devices can also withstand higher bus voltage in comparison to GaN cascode devices when under electrothermal stress by unclamped inductive switching. The analysis of transfer characteristics and leakage current of SiC JFET & GaN HEMT cascode structures following UIS stress have also been performed together with Computed Tomography (CT) Scan imaging to determine the per-area avalanche energy density.
•The UIS test is performed at different voltages, temperatures and pulse lengths to observe the avalanche capability of the cascode devices.•The results illustrates that the SiC cascode has higher avalanche energy capability than the GaN device.•The SiC device also has a higher avalanche energy density per area than the GaN Cascode.•The current capability in GaN is almost half of that of the SiC device while the SiC cascode can withstand larger bus voltages.