Details

Autor(en) / Beteiligte

• Wang Qian
• Wang Pengjun
• Gong Daohui

Titel

Novel low-power ternary explicit pulsed JKL flip-flop based on CNFET

Ist Teil von

• 2016 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB), 2016, p.1-4

Ort / Verlag

IEEE

Erscheinungsjahr

2016

Link zum Volltext

• Volltext

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A novel single-edge explicit pulsed JKL flip-flop (S-JKL) and dual-edge explicit pulsed JKL flip-flop (D-JKL) are designed with Carbon Nanotube Field Effect Transistor (CNFET). Firstly, a single-edge pulsed generator (S-PG) is designed. Then combined with a ternary JKL latch, a S-JKL is obtained; D-JKL is designed by replacing S-PG with double-edge pulsed generator (D-PG). The circuits possess the character of high speed and low power by employing CNFET. The scheme is simulated by HSPICE, and the results show that the designed ternary explicit pulsed JKL flip-flop has correct logic function and low power consumption.