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Efficient routing in network-on-chip for 3D topologies
Ist Teil von
International journal of electronics, 2015-10, Vol.102 (10), p.1695-1712
Ort / Verlag
Abingdon: Taylor & Francis
Erscheinungsjahr
2015
Link zum Volltext
Quelle
Alma/SFX Local Collection
Beschreibungen/Notizen
With the increasing of the integration capability intra-chip, nowadays numerous integrated systems explore a set of processing elements, such as in multicore processors. An efficient interconnection of those elements can be obtained via the use of Network on chip (NoC). This approach is similar to the traditional computer networks where, not restricted to multiprocessors, it is possible to interconnect several dedicated devices. Like other networks, NoCs can be arranged in different topologies, such as ring, mesh and torus. It has shared links that can be used in the transmission of packets of different nodes. Thus, the network congestion is an issue and must be treated to reduce delays. Algorithms based on ant colony optimisation have proven to be effective in static routing in systems designed to perform a fixed set of tasks, or where the communication pattern is known. This article introduces 3D ant colony routing (3D-ACR) and applies it as routing policy of NoCs having three different 3D topologies: mesh, torus and hypercube. Experimental results show that 3D ant colony routing performs consistently better compared with the previously proposed routing strategies.