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In this article, we present static random access memory (SRAM) write- and performance-assist cells (W- and P-ACs, respectively) that can effectively resolve the degradation in writeability and performance due to the increase in interconnect resistance with technology scaling. The proposed W- and P-ACs have bit-cell compatible layouts, and thus, they can be inserted into a bit-cell array without white space. Given that bit-line (BL) and BL-bar (BLB) are driven in parallel by the write driver (WD) and proposed W-AC, the effective BL resistance <inline-formula> <tex-math notation="LaTeX">(R_{\mathbf {BL}} </tex-math></inline-formula>) is reduced. This, in turn, leads to an improvement in writeability. In addition, the proposed P-AC accelerates word-line (WL) by sensing WL rising voltage and, thus, improves the read access time on the bit-cell located far from the WL driver. To measure the interconnect resistance effects, 32-kb SRAM macros with poly resistors were fabricated on 28-nm CMOS technology. The proposed W-AC achieves 100% writeability yield not only in the 3-nm resistance model but also in the sub-3-nm resistance model, while the writeability yield of the conventional scheme with a single WD decreased to <inline-formula> <tex-math notation="LaTeX">2.3\sigma </tex-math></inline-formula> in the 3-nm resistance model. The proposed P-AC reduced the read access time by 28% compared with that of the conventional scheme with a single WL driver in the 3-nm resistance model.