Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
Two advanced energy-back SAR ADC architectures with 99.21 and 99.37 % reduction in switching energy
Ist Teil von
Analog integrated circuits and signal processing, 2016-04, Vol.87 (1), p.81-91
Ort / Verlag
New York: Springer US
Erscheinungsjahr
2016
Link zum Volltext
Quelle
Alma/SFX Local Collection
Beschreibungen/Notizen
This letter presents novel energy-efficient switching schemes for a successive approximation register analog-to-digital converter. The new switch method consumes no switching energy in the first three comparison cycles. The average switching energy is reduced by 99.21 and 99.37 % for the signal-independent and signal-dependent common mode voltage at the comparator, respectively. A 75 % reduction in the total capacitance over the conventional scheme is also achieved. The variation of the common mode voltage at the comparator input in the proposed architecture is 50 % less than in other low power switching schemes.