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SAR ADC architecture with 98.8 % reduction in switching energy over conventional scheme
Ist Teil von
Analog integrated circuits and signal processing, 2015-07, Vol.84 (1), p.89-96
Ort / Verlag
New York: Springer US
Erscheinungsjahr
2015
Link zum Volltext
Quelle
Alma/SFX Local Collection
Beschreibungen/Notizen
A novel power saving switching scheme for successive approximation register analogue-to-digital converter is proposed in this letter. Adopting the top-plated sampling technology and dummy-capacitor-aided switching technology, the number of capacitors can be reduced by 75 % compared with the conventional scheme. Employing the one-side switching instead technology and higher-bit switching instead technology, the average switching energy can be reduced to 1.2 % compared with the conventional scheme. Employed the proposed switching scheme, a 10-bit 20-kS/s 0.6-V SAR ADC is designed in 0.18-μm CMOS technology. Post-layout simulation results indicate that a SNDR of 60.3 dB can be achieved with the Nyquist input at 20 kS/s. And the figure-of-merit of the proposed ADC is 1.04 fJ/conversion-step.