Details

Autor(en) / Beteiligte

• Ungerer, Theo
• Zehendner, Eberhard

Titel

Threads and subinstruction level parallelism in a data flow architecture

Ist Teil von

• Parallel Processing: CONPAR 92—VAPP V, 2005, p.731-736

Ort / Verlag

Berlin, Heidelberg: Springer Berlin Heidelberg

Erscheinungsjahr

2005

Link zum Volltext

Quelle

Alma/SFX Local Collection

Beschreibungen/Notizen

• This paper presents a data flow architecture that utilizes task level parallelism by the architectural structure of a distributed memory multiprocessor, instruction level parallelism by a token-passing computation scheme, and subinstruction level parallelism by SIMD evaluation of complex machine instructions. Sequential threads of data instructions are compiled to data flow macro actors and executed consecutively using registers.