Details

Autor(en) / Beteiligte

• Leon, Vasileios
• Xydis, Sotirios
• Soudris, Dimitrios
• Pekmestzi, Kiamal

Titel

Energy-efficient VLSI implementation of multipliers with double LSB operands

Ist Teil von

• IET circuits, devices & systems, 2019-09, Vol.13 (6), p.816-821

Ort / Verlag

Stevenage: The Institution of Engineering and Technology

Erscheinungsjahr

2019

Quelle

Wiley Online Library Journals Frontfile Complete

Beschreibungen/Notizen

• Multiplication is an arithmetic operation that has a significant impact on the performance of various real-life applications, such as digital signal processing, image processing and computer vision. In this study, targeting to exploit the efficiency of alternative number representation formats, the authors propose an energy-efficient scheme for multiplying 2's-complement binary numbers with two least significant bits (LSBs). The double-LSB (DLSB) arithmetic delivers several benefits, such as the symmetric representation range, the number negation performed only by bitwise inversion, and the facilitation of the rounding process in the results of floating point architectures. The hardware overhead of the proposed circuit, when implemented at 45 nm, is negligible in comparison with the conventional Modified Booth multiplier for the ordinary 2's-complement numbers (3.1% area and 3.3% energy average overhead for different multiplier's bit-width). Moreover, the proposed DLSB multiplier outperforms the previous state-of-the-art implementation by providing 10.2% energy and 7.8% area average gains. Finally, they demonstrate how the DLSB multipliers can be effectively used as a building block for the implementation of larger multiplications, delivering area and energy savings.