Autor(en)
Zhu, Zhengyun; Ren, Na; Xu, Hongyi; Liu, Li; Sheng, Kuang
Titel
Characterization and Analysis on Performance and Avalanche Reliability of SiC MOSFETs With Varied JFET Region Width
Teil von
  • IEEE transactions on electron devices, 2021-08, Vol.68 (8), p.3982-3990
Ort / Verlag
IEEE
Links zum Volltext
Quelle
IEEE Electronic Library (IEL) Journals
Beschreibungen
In this work, the influence of JFET region width on device's performance and avalanche reliability is studied on 1200 V planar-gate silicon carbide (SiC) MOSFETs fabricated on a 4-in SiC wafer. Unclamped inductive switching (UIS) test is conducted to compare the devices under tests (DUTs) avalanche capability at both <inline-formula> <tex-math notation="LaTeX">{V}_{\text {GS}} ={0} </tex-math></inline-formula> V and <inline-formula> <tex-math notation="LaTeX">{V}_{\text {GS}} = -5 </tex-math></inline-formula> V. At <inline-formula> <tex-math notation="LaTeX">{V}_{\text {GS}} ={0} </tex-math></inline-formula> V, the best avalanche reliability is achieved with a JFET region width of <inline-formula> <tex-math notation="LaTeX">{4}~\mu \text{m} </tex-math></inline-formula>. Through mix-mode TCAD simulation, channel conduction is found to contribute to the failure at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {GS}} ={0} </tex-math></inline-formula> V. While at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {GS}} =-5 </tex-math></inline-formula> V, the best avalanche reliability is achieved with a JFET region width ranging from 2 to <inline-formula> <tex-math notation="LaTeX">{3}~\mu \text{m} </tex-math></inline-formula>. Hole injection is observed in the test and recognized in simulation, which critically influences the DUTs' avalanche reliability at <inline-formula> <tex-math notation="LaTeX">{V}_{\text {GS}} = -5 </tex-math></inline-formula> V.
Format
Sprache(n)
Englisch
Identifikator(en)
ISSN: 0018-9383
ISSN: 1557-9646
DOI: 10.1109/TED.2021.3091043

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