Details

Autor(en) / Beteiligte

• de Prado, Miguel
• Mundy, Andrew
• Saeed, Rabia
• Denna, Maurizo
• Pazos, Nuria
• Benini, Luca

Titel

Automated Design Space Exploration for Optimized Deployment of DNN on Arm Cortex-A CPUs

Ist Teil von

• IEEE transactions on computer-aided design of integrated circuits and systems, 2021-11, Vol.40 (11), p.2293-2305

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2021

Quelle

IEEE Xplore

Beschreibungen/Notizen

• The spread of deep learning on embedded devices has prompted the development of numerous methods to optimize the deployment of deep neural networks (DNNs). Works have mainly focused on: 1) efficient DNN architectures; 2) network optimization techniques, such as pruning and quantization; 3) optimized algorithms to speed up the execution of the most computational intensive layers; and 4) dedicated hardware to accelerate the data flow and computation. However, there is a lack of research on cross-level optimization as the space of approaches becomes too large to test and obtain a globally optimized solution. Thus, leading to suboptimal deployment in terms of latency, accuracy, and memory. In this work, we first detail and analyze the methods to improve the deployment of DNNs across the different levels of software optimization. Building on this knowledge, we present an automated exploration framework to ease the deployment of DNNs. The framework relies on a reinforcement learning search that, combined with a deep learning inference framework, automatically explores the design space and learns an optimized solution that speeds up the performance and reduces the memory on embedded CPU platforms. Thus, we present a set of results for state-of-the-art DNNs on a range of Arm Cortex-A CPU platforms achieving up to <inline-formula> <tex-math notation="LaTeX">4\times </tex-math></inline-formula> improvement in performance and over <inline-formula> <tex-math notation="LaTeX">2\times </tex-math></inline-formula> reduction in memory with negligible loss in accuracy with respect to the BLAS floating-point implementation.