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IEEE transactions on electron devices, 2020-06, Vol.67 (6), p.2276-2281
2020

Details

Autor(en) / Beteiligte
Titel
Drain Current Optimization in DIBS-Grown MgZnO/CdZnO HFET
Ist Teil von
  • IEEE transactions on electron devices, 2020-06, Vol.67 (6), p.2276-2281
Ort / Verlag
IEEE
Erscheinungsjahr
2020
Link zum Volltext
Quelle
IEEE/IET Electronic Library
Beschreibungen/Notizen
  • This article reports the fabrication of a dual-ion beam sputtering (DIBS)-grown MgZnO/CdZnO (MCO)-based gateless heterostructure field-effect transistor (HFET). In addition, this article presents that by introducing a 30-nm yttria spacer layer, the crystallinity of the CdZnO buffer layer can be enhanced and the interface roughness at the heterojunction of the MCO heterostructure can be reduced. Furthermore, the source and drain metal contacts were optimized for the least specific contact resistivity (<inline-formula> <tex-math notation="LaTeX">\boldsymbol {\rho }_{c} </tex-math></inline-formula>) yielding metal combination and annealing conditions. The results suggest that the introduction of the yttria spacer layer improves the overall conductance [product of sheet carrier density (<inline-formula> <tex-math notation="LaTeX">{n}_{s} </tex-math></inline-formula>) and electron mobility (<inline-formula> <tex-math notation="LaTeX">\boldsymbol {\mu } </tex-math></inline-formula>)] of MCO up to <inline-formula> <tex-math notation="LaTeX">3.5\times 10^{15}\,\,\text{V}^{-1}\text{s}^{-1} </tex-math></inline-formula> compared to <inline-formula> <tex-math notation="LaTeX">9\times 10^{14}\,\,\text{V}^{-1}\text{s}^{-1} </tex-math></inline-formula> in the non-yttria spacer-based MCO. In addition, the drain current (<inline-formula> <tex-math notation="LaTeX">{I}_{d} </tex-math></inline-formula>)-drain voltage (<inline-formula> <tex-math notation="LaTeX">{V}_{d} </tex-math></inline-formula>) characteristic of the as-developed yttria spacer-based MCO HFET shows a high drain current value (~400 mA/mm). These results establish the DIBS-grown MCO heterostructure as a viable option for low-cost HFETs necessary for the fabrication of large-scale HFET-based power and sensor devices.
Sprache
Englisch
Identifikatoren
ISSN: 0018-9383
eISSN: 1557-9646
DOI: 10.1109/TED.2020.2989731
Titel-ID: cdi_ieee_primary_9090339

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