Details

Autor(en) / Beteiligte

• Tripathi, Suman Lata
• Verma, Shekher
• Patel, Govind Singh

Titel

Subthreshold Performance Evaluation of JLDG-MOSFET

Ist Teil von

• 2019 5th International Conference on Signal Processing, Computing and Control (ISPCC), 2019, p.181-184

Ort / Verlag

IEEE

Erscheinungsjahr

2019

Quelle

IEEE Xplore

Beschreibungen/Notizen

• A new high performance Junction-less double gate MOSFET (JLDG-MOSFET) is proposed for gate length 20nm with performance analysis in terms of Io N /I OFF (~10 7 ) ratio and subthreshold slope(mV/decade) and DIBL(mV/V) in comparison to existing DG-MOSFET structure. The analysis of JLDG-MOSFET is carried out for DC parameters at room temperature (300K). The proposed JLDG-MOSFET exploits the junction-less behavior that supports reasonable value of ON/OFF currents as well as improved subthreshold parameters. The analysis of JLDG-MOSFET is carried out for DC parameters at room temperature. The ON and OFF-state performance of the proposed device is carried out with varying doping, oxide thickness and gate dielectric constant. All the proposed JLDG-MOSFET has been implemented with 2D and 3D Visual-TCAD device simulator.