Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
Rapid single flux quantum (RSFQ) logic, based on Josephson junctions (JJs), is seeing a resurgence as a way for providing high performance in the era beyond the end of physical scaling of complementary metal-oxide-semiconductor (CMOS). Due to its use of fabrication processes with large feature sizes, the defect density for RSFQ is lower than its CMOS counterpart. Hence, process variations and other RSFQ-specific nonidealities are major causes of chip failures. Because of the nature of its quantized pulse-based operation, even highly distorted pulses are interpreted logically correctly by cells, but the timings are affected. Therefore, timing verification and delay testing increase in importance in RSFQ. Our goal is to ensure that designs and fabricated chips provide desired performance. To achieve this goal, we propose new methods and tools for timing verification and delay testing of fully path balanced RSFQ logic circuits that use concurrent-flow clocking scheme. We address several radically new phenomena in the RSFQ technology, especially the existence of single-pattern delay tests and the need to propagate delayed values via multiple pipeline stages. We then characterize cells under process variations and identify delay excitation conditions, sensitization conditions, and conditions for propagation of the logic errors caused by timing violations due to process variations. We then propose a completely new paradigm for automatic test pattern generation (ATPG) which utilizes these new phenomena to select multicycle paths as targets and to generate test patterns that are guaranteed to excite the worst-case delay along each target multicycle path. Finally, we present theoretical proofs and Monte Carlo simulation results for benchmark circuits under process variations to demonstrate that the patterns generated by our new ATPG are effective (invoke maximum delays of target multicycle paths) and efficient (require small numbers of patterns).