Sie befinden Sich nicht im Netzwerk der Universität Paderborn. Der Zugriff auf elektronische Ressourcen ist gegebenenfalls nur via VPN oder Shibboleth (DFN-AAI) möglich. mehr Informationen...
    Datensatz exportieren als...
  • BibTeX
Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects
IEEE transactions on electron devices, 2019-11, Vol.66 (11), p.4653-4659
2019

Details

Autor(en) / Beteiligte
Titel
Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects
Ist Teil von
  • IEEE transactions on electron devices, 2019-11, Vol.66 (11), p.4653-4659
Ort / Verlag
New York: IEEE
Erscheinungsjahr
2019
Link zum Volltext
Quelle
IEEE Xplore
Beschreibungen/Notizen
  • In this article, an analytical predictive model of interface charge traps in symmetric, long-channel double-gate, junctionless transistors (JLTs) is proposed based on a charge-based model. Interface charge traps arising from exposure to chemicals, high-energy ionizing radiation, or aging mechanism could degrade the charge-voltage characteristics. The model is predictive in a range of temperatures from 77 to 400 K. The validity of the approach is confirmed by extensive comparisons with numerical technology computer-aided design (TCAD) simulations in all regions of operation from deep depletion to accumulation and from linear to saturation.
Sprache
Englisch
Identifikatoren
ISSN: 0018-9383
eISSN: 1557-9646
DOI: 10.1109/TED.2019.2944193
Titel-ID: cdi_ieee_primary_8866757
Format
–
Schlagworte
Aging effects, biosensors, CAD, charge-based model, Computational modeling, Computer aided design, Computer simulation, Depletion, double-gate junctionless field-effect transistor (DG JLFET), Electric potential, Electron traps, Energy states, Field effect transistors, interface traps, Ionizing radiation, Logic gates, MOSFET, Organic chemistry, temperature, Temperature effects

Weiterführende Literatur

Empfehlungen zum selben Thema automatisch vorgeschlagen von bX