Details

Autor(en) / Beteiligte

• Ali, Muhammad
• Abrar Ahmed, Mohammed
• Chrzanowska-Jeske, Malgorzata

Titel

Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization

Ist Teil von

• IEEE transactions on very large scale integration (VLSI) systems, 2019-03, Vol.27 (3), p.573-586

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2019

Link zum Volltext

• Volltext

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• Carbon nanotube field-effect transistors (CNFETs) show great potential to build digital systems on advanced technology nodes with big benefits in terms of power, performance, and area (PPA). However, CNFET-specific additional features such as the number of tubes, pitch (spacing between tubes), tube position, and diameter in array of tubes play a significant role in accurate PPA evaluation. Furthermore, count and density variations in carbon nanotubes (CNTs) due to manufacturing limitations, like the presence of metallic tubes in the CNFET channel, degrade the anticipated PPA benefits. Moreover, modeling the CNFET parameters, CNT variations and etching techniques for CNTs create additional complexity during performance optimization. Hence, for realistic optimization of CNFET circuit's performance, it is imperative to incorporate the impact of these parameters and variations. In this paper, we propose delay models [pitch-aware logical effort (PALE) and position-aware pitch factor (PAPF)] for fast and accurate performance evaluation by including the impact due to CNFET-specific parameters and CNT variations. These models are developed based on industry standard logical effort framework. Furthermore, we present an optimization tool using PALE and PAPF to minimize the delay and area of CNFET circuits. We deploy several circuit-level techniques prior to optimizing the tubes (CNTs) in the logic gates to achieve globally optimum solution. For better optimization of the circuits, we also include the impact of wire parasitic in estimating the delay of the individual gates. Our optimization tool results in the maximum and average delay improvement by 27% and 17%, respectively, and <inline-formula> <tex-math notation="LaTeX">2.5\times </tex-math></inline-formula> reduction in area for standard ISCAS and OpenSPARC benchmark circuits. Fast and fairly accurate delay computation in our optimization framework offers great runtime benefits as compared to state-of-the-art simulation and statistical-based methods.