UB Paderborn / Katalog / Details

IEEE transactions on electron devices, 2017-09, Vol.64 (9), p.3534-3540

2017

Autor(en) / Beteiligte

Titel

A Threshold Voltage Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects

Ist Teil von

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2017

Link zum Volltext

Quelle

IEEE Xplore

Beschreibungen/Notizen

In this paper, the influence of substrate bias voltage and substrate-induced surface potential (SISP) on threshold voltage of tri-gate junctionless field-effect transistors (TG-JLFETs) has been investigated. For this purpose, a quasi-3-D threshold voltage model of TG-JLFETs is presented considering the effects of both back-bias voltage and a lightly doped substrate. To incorporate the effect of SISP on the threshold voltage, the boundary conditions at the silicon-buried oxide interface have been modified accounting for the potential difference between substrate surface and substrate bulk. Model results are compared with the simulation results obtained using 3-D visual TCAD device simulator from Cogenda.

Sprache: Englisch
Identifikatoren: ISSN: 0018-9383
eISSN: 1557-9646
DOI: 10.1109/TED.2017.2722044
Titel-ID: cdi_ieee_primary_7976324

Format: –
Schlagworte: Bias, Boundary conditions, Computer simulation, Drain-induced barrier lowering (DIBL), Electric potential, Field effect transistors, junctionless field-effect transistor (JLFET), Logic gates, Plasma, Semiconductor devices, Silicon, substrate bias, Substrates, Three dimensional models, Threshold voltage, Transistors, tri-gate (TG)

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