Details

Autor(en) / Beteiligte

• Sahay, Shubham
• Kumar, Mamidala Jagadesh

Titel

Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core-Shell Architecture

Ist Teil von

• IEEE transactions on electron devices, 2016-09, Vol.63 (9), p.3790-3794

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2016

Link zum Volltext

• Volltext

Quelle

IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• In this paper, we propose the use of a p + core in the core-shell nanowire (CS NW) architecture to significantly reduce the gate induced drain leakage and therefore, increase the ON-state to OFF-state current ratio (I ON /I OFF ) in n-NW junctionless FETs (NWJLFETs). We show that the lateral bandto-band tunneling induced parasitic bipolar junction transistor action is diminished in the CSJLFET due to an enhanced tunneling width and a higher source to channel barrier height. Further, we also demonstrate that the p + core helps to realize efficient volume depletion in NWJLFETs with large NW width. Using calibrated 3-D simulations, we show that the CSJLFET exhibits a significantly high ON-state to OFF-state current ratio (I ON /I OFF ) of ~10 7 even for a channel length of 7 nm.