Details

Autor(en) / Beteiligte

• Sanyal, Indraneel
• Lin, En-Shuo
• Wan, Yu-Chen
• Chen, Kun-Ming
• Tu, Po-Tsung
• Yeh, Po-Chun
• Chyi, Jen-Inn

Titel

AlInGaN/GaN HEMTs With High Johnson's Figure-of-Merit on Low Resistivity Silicon Substrate

Ist Teil von

• IEEE journal of the Electron Devices Society, 2021, Vol.9, p.130-136

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2021

Link zum Volltext

Quelle

EZB Free E-Journals

Beschreibungen/Notizen

• This work demonstrates high-performance AlInGaN/AlN/GaN high electron mobility transistors grown on 150 mm p-type low resistivity (resistivity~ 20-100 <inline-formula> <tex-math notation="LaTeX">\Omega </tex-math></inline-formula>-cm) silicon substrate with state-of-the-art Johnson's figure-of-merit (JFOM). Current gain cut-off frequency (<inline-formula> <tex-math notation="LaTeX">\text{f}_{\mathrm{ T}} </tex-math></inline-formula>) of 83 GHz and 63 GHz and power gain cut-off frequency (<inline-formula> <tex-math notation="LaTeX">\text{f}_{\mathrm{ max}} </tex-math></inline-formula>) of 95 GHz and 77 GHz with a three-terminal off-state breakdown voltage of 69 V and 127 V, resulting in a high JFOM of 5.7 THz-V and 8.1 THz-V are achieved on the devices with a gate length of 0.16 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> and gate to drain distance of 2 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula> and 4 <inline-formula> <tex-math notation="LaTeX">\mu \text{m} </tex-math></inline-formula>, respectively. The <inline-formula> <tex-math notation="LaTeX">\text{f}_{\mathrm{ T}} </tex-math></inline-formula> and J-FOM are comparable or better than the reported values obtained on high resistivity silicon and SiC substrates for devices with similar gate length. On the other hand, GaN-on-Si HEMT structure on the LR-Si substrate exhibits lower power gain and power added efficiency due to strong capacitive coupling effects. TCAD large signal output power simulation indicates significant improvements in output power by minimizing the defects and free charge carriers in the GaN buffer even in the presence of the parasitic channel conduction and conductive silicon substrate. We further propose a modified equivalent circuit model of the parasitic conduction to take into account the conductivity of the GaN and AlGaN buffer.