Details

Autor(en) / Beteiligte

• Nowatzki, Tony
• Gangadhar, Vinay
• Sankaralingam, Karthikeyan
• Wright, Greg

Titel

Pushing the Limits of Accelerator Efficiency While Retaining Programmability

Ist Teil von

• IEEE MICRO, 2017-06, p.1-1

Ort / Verlag

IEEE

Erscheinungsjahr

2017

Link zum Volltext

• Volltext

Quelle

IEEE Xplore

Beschreibungen/Notizen

• The waning benefits of device scaling have caused a pushtowards domain specific accelerators (DSAs), which sacrificeprogrammability for efficiency, are prone to obsoletion dueto domain volatility, and have recurring design and verificationcosts. Because of the benefits of generality, this workexplores how far a programmable architecture can be pushed,and whether it can come close to the performance, energy,and area efficiency of a DSA-based approach. We discoverthat DSAs employ common specialization principles forconcurrency, computation, communication, data-reuse andcoordination, and that these same principles can be exploitedin a programmable architecture using a composition ofknown microarchitectural mechanisms. Specifically, wepropose and study an architecture called LSSD, which iscomposed of many low-power and tiny cores, each havinga configurable spatial architecture, scratchpads, and DMAengine. Our results show that a programmable, specializedarchitecture can indeed be competitive with a domain-specificapproach. Compared to four diverse and prominentDSAs (three of which were TopPicks selections themselves,and one was in CACM Research Highlights), LSSD canmatch the DSAs' 10x to 150x speedup over an OOO core,with only up to 4x more area and power than a single DSA,while retaining programmability.