Details

Autor(en) / Beteiligte

• Yano, Koji
• Tanaka, Yasunori
• Yamamoto, Masayuki

Titel

Extremely Low ON-Resistance SiC Cascode Configuration Using Buried-Gate Static Induction Transistor

Ist Teil von

• IEEE electron device letters, 2018-12, Vol.39 (12), p.1892-1895

Ort / Verlag

New York: IEEE

Erscheinungsjahr

2018

Link zum Volltext

• Volltext

Quelle

IEEE Electronic Library Online

Beschreibungen/Notizen

• A 35-A cascode configuration of a drain-to-source breakdown voltage of 978 V utilizing an silicon carbide (SiC) buried gate static induction transistor (BGSIT) and low voltage Si-MOSFET (SiC-BGSIT cascode) has been experimentally demonstrated for the first time. The SiC-SIT is mounted with the Si-MOSFET in an originally designed resin 4pin package. The ON-resistance <inline-formula> <tex-math notation="LaTeX">R_{\text {DS(ON)}} </tex-math></inline-formula> of this device exhibits 34.3 <inline-formula> <tex-math notation="LaTeX">\text{m}\Omega </tex-math></inline-formula> at room temperature, which is 50% of the commercial SiC MOSFET of the similar rating. The temperature dependence of <inline-formula> <tex-math notation="LaTeX">R_{\text {DS(ON)}} </tex-math></inline-formula> and gate threshold voltage has been revealed. It has been suggested that when compared with the SiC-JFET cascode with the similar rating, the BGSIT cascode has a soft <inline-formula> <tex-math notation="LaTeX">\textit {dV}_{\text {ds}}/\textit {dt} </tex-math></inline-formula> property with a relatively small switching loss.