Details

Autor(en) / Beteiligte

• Nolet, F
• Roy, N
• Carrier, S
• Bouchard, J
• Fontaine, R
• Charlebois, S.A
• Pratte, J.-F

Titel

22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time-to-digital converter in CMOS 65 nm for single photon avalanche diode array

Ist Teil von

• Electronics letters, 2020-04, Vol.56 (9), p.424-426

Ort / Verlag

The Institution of Engineering and Technology

Erscheinungsjahr

2020

Link zum Volltext

Quelle

Free E-Journal (出版社公開部分のみ）

Beschreibungen/Notizen

• A Vernier ring-oscillator-based time-to-digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of $0.00151\,{\rm mm}^2$0.00151mm2. Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to $22\,{\rm \mu }{\rm W}$22μW at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission tomography single photon avalanche diode based detectors.