Details

Autor(en) / Beteiligte

• Ho, Tsung-Yi,
• Hu, Shiyan,
• Badaroglu, Mustafa,

Titel

2017 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)

Ort / Verlag

Piscataway, N.J. : IEEE,

Erscheinungsjahr

2017

Beschreibungen/Notizen

• High speed chip to chip interconnect design Design and analysis of chip package interfaces Power consumption of interconnects 3D interconnect design and prediction Emerging interconnect technologies Applications of interconnects to social, genetic, and biological systems Co optimization of interconnect technology and chip design High speed chip to chip interconnect design Design and analysis of chippackage interfaces Power consumption of interconnects 3D interconnect design and prediction Emerging interconnect technologies Applications of interconnects to social, genetic, and biological systems Co optimization of interconnect technology and chip design.
• Description based on publisher supplied metadata and other sources.