Details

Autor(en) / Beteiligte

• IEEE, Electron Devices Society Staff

Titel

2000 IEEE International Electron Devices Meeting

Ort / Verlag

[Place of publication not identified] : I E E E

Erscheinungsjahr

2000

Link zum Volltext

• IEEE Electronic Library (IEL)

Beschreibungen/Notizen

• Bibliographic Level Mode of Issuance: Monograph
• PLENARY SESSION -- Microsystems for the Automotive Industry / Matthias Illing -- III-V Nitride-based LEDs and Lasers: Current Status and Future Opportunities / Shuji Nakamura -- Prospects for Quantum Computing / David DiVincenzo -- Session 2: Process Technology-Gate Dielectrics-Zr and Hf Oxides / Vivek Subramanian -- Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Depostion / N. Fukushima A. Toriumi -- Si-Doped Aluminates for High Temperature Metal-Gate CMOS: Zr-Al-Si-O, A Novel Gate Dielectric for Low Power Applications / H. Schulte -- MOS Characteristics of Ultra Thin Rapid Thermal CVD ZrO2 and Zr Silicate Gate Dielectrics / D.L. Kwong -- High Quality Untra Thin CVD HfO2 Gate Stack with Poly-Si Gate Electrode / D.L. Kwong -- MOSFET Devices with Polysilicon on Single-Layer HfO2 High-K Dielectrics / J.C. Lee -- Characteristics of TaN Gate MOSFET with Ultrathin Hafnium Oxide (8A-12A) / J.C. Lee -- Session 3: CMOS Devices-Sub-50nm Devices / Clement Wann -- 30nm Physical Gate Length CMOS Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delays / G. Dewey -- 45-nm Gate Length CMOS Technology and Beyond using Steep Halo / T. Kunio -- SALVO Process for Sub-50 nm Low-VT Replacement Gate CMOS with KrF Lithography / J.T.-C. Lee -- Complementary Silicide Source/Drain Thin-Body MOSFETs for the 20nm Gate Length Regime / C. Hu -- 50-nm Vertical Sidewall Transistors with High Channel Doping Concentrations / U. Langmann -- 50-nm Vertical Replacement-Gate (VRG) pMOSFETs / J. Plummer -- Session 4: Solid State Devices-Power Device Technology / Jack Lau -- Vertical Power-MOSFETs with Local Channel Doping / W. Kanert -- SOA Improvement by a Double RESURF LDMOS Technique in a Power IC Technology / A. Bose -- Temperature Dependence of Avalanche Multiplication in Spiked Electric Fields / J.W. Slotboom -- Electrical-Thermal Coupling Mechanism on Operating Limit of LDMOS Transistor / B. Baird -- Reduction of Metal-Semiconductor Contact Resistance by Embedded Nanocrystals / E.C. Kan -- Session 5: Modeling and Simulation-Hot Carrier and Transport Modeling / Jeff Bude -- Simulation of Si-SiO2 Defect Generation in CMOS Chips: from Atomistic Structure to Chip Failure Rates (Invited) / J. Lyding -- Impact Ionization and Photon Emission in MOS Capacitors and FETs / E. Sangiorgi -- An Accurate, Experimentally Verified Electron Minority Carrier Mobility Model for Si and SiGe / B. Meinerzhagen -- Enhanced Secondary Electron Injection in Novel SiGe Flash Memory Devices / S. Banerjee -- Efficiency and Stochastic Error of Monte Carlo Device Simulations / B. Meinerzhagen -- Ensemble Monte Carlo/Molecular Dynamics Simulation of Gate Remote Charge Effects in Small Geometry MOSFETs / K. Taniguchi -- Session 6: CMOS and Interconnect Reliability-Reliability of Advanced Technologies / Sorin Cristoloveanu -- Optimizing the Electromigration Performance of Copper Interconnects (Invited) / H. Kawasaki -- Improvement of Thermal Stability of Via Resistance in Dual Damascene Copper Interconnection / K. Hinode -- ESD Protection Scheme Using CMOS Compatible Vertical Bipolar Transistor For 130nm CMOS Generation / N. Ikezawa -- Reliability Issues for Silicon-on-Insulator (Invited) / D. Badami -- Hot Carrier Reliability for 0.13[MARC+6F]m CMOS Technology with Dual Gate Oxide Thickness / R. Mahnkopf -- Valence-Band Tunneling Enhanced Hot Carrier Degradation in Ultra-Thin Oxide nMOSFETs / L.C. Hsia -- Session 7: Integrated Circuits and Manufacturing-Analog/RF and 3D ICs / Makoto Yoshida -- COM2 SiGe Modular BiCMOS Technology for Digital, Mixed-Signal, and RF Applications / W. Wu -- A 73GHz fT 0.18[MARC+6F]m RF-SiGe BiCMOS Technology Considering Thermal Budget Trade-off and with Reduced Boron-Spike Effect on HBT Characteristics / T. Yamazaki -- Integration of Thin Film MIM Capacitors and Resistors into Copper Metalization Based RF-CMOS and Bi-CMOS Technologies / M. Miller -- A High Reliability Metal Insulator Metal Capacitor for 0.18 [MARC+6F]m Copper Technology / K. Stein -- Three Dimensional CMOS Integrated Circuits on Large Grain Polysilicon Films / M. Chan -- Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology / M. Koyanagi -- Novel Silicon Epitaxy for Advanced MOSFET Devices (Invited) / J. Denton -- Session 8: Quantum Electronics and Compound Semiconductors-High Speed Compound Semiconductor Devices / Youngwoo Kwon -- InP HEMT Amplifier Development for G-band (140-220 GHz) Applications (Invited) / D. Streit -- Abrupt Junction InP/GaAsSb/InP Double Hetero-junction Bipolar Transistors with FT as High as 250 GHz and BVCEO>6V / C. Bolognesi -- Metamorphic HFETs on GaAs with InP-Subchannels for Device Performance Improvements / E. Kohn -- Simulation of InAIAs/InGaAs High Electron Mobility Transistors with a Single Set of Physical Parameters / S. Selberherr -- Reliability Study of Parasitic Source and Drain Resistances of InP-Based HEMTs / H. Yokoyama -- Session 9: Detectors, Sensors and Displays-Si Thin Film Transistors / Henning Sirringhaus -- Low Temperature Poly-Si TFT-Electrophoretic Displays (TFT-EPDs) with Four Level Gray Scale / T. Shimoda -- High Density, Low Parasitic Direct Integration by Fluidic Self Assembly (FSA) (Invited) / J. Smith -- A New Dopant Activation Technique for Poly-Si TFTs with a Self-Aligned Gate-Overlapped LDD Structure / N. Sasaki -- Selective Single-Crystalline-Silicon Growth at the Pre-Defined Active Regions of TFTs on a Glass by a Scanning CW Laser Irradiation / N. Sasaki -- A New Poly-Si TFT with Selectively Doped Channel Fabricated by Novel Excimer Laser Annealing / M.-K. Han -- Reliability of Low Temperature Poly-Si TFT Employing Counter-Doped Lateral Body Terminal / H.J. Kim -- Session 10: CMOS Devices-Device Scaling / Yasuo Inoue -- 80 nm Poly-Silicon Gated n-FETs with Ultra-Thin Al2O3 Gate Dielectric for ULSI Applications / R. Arndt -- Extending Gate Dielectric Scaling Limit by NO Oxynitride: Design and Process Issues for Sub-100 nm Technology / Y. Toyoshima -- Controlling Floating-Body Effects for 0.13[MARC+6F]m and 0.10[MARC+6F]m SOI CMOS / G. Shahidi -- CMOS Device Scaling Beyond 100nm (Invited) / M.Y. Lee -- 80nm CMOSFET Technology Using Double Offset-Implanted Source/Drain Extension and Low Temperature SiN Process / M. Inuishi -- Source/Drain Engineering for Sub-100 nm CMOS Using Selective Epitaxial Growth Technique / Y. Toyoshima -- Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design / T. Horiuchi -- Session 11: Process Technology-Advanced Interconnect Technology / Hans-Joachim Barth -- Current and Future Low-k Dielectrics for Cu Interconnects (Invited) / T. Kikkawa -- Process Design Methodology for Via-Shape-Controlled, Copper Dual-Damascene Interconnects in Low-k Organic Film / Y. Hayashi -- Withdrawn -- Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects / K. Saraswat -- A High Reliability Copper Dual-Damascene Inter-connection with Direct-Contact Via Structure / S. Saito -- Session 12: Modeling and Simulation-Quantum and Atomic Scale Effects in MOSFETs / Robert Dutton -- Vth Fluctuation Induced by Statistical Variation of Pocket Dopant Profile / T. Sugii -- Role of Long-Range and Short-Range Coulomb Potentials in Threshold Characteristics under Discrete Dopants in Sub-0.1 [MARC+6F]m Si-MOSFETs / N. Nakayama -- Random Telegraph Signal Amplitudes in Sub 100 nm (Decanano) MOSFETs: A 3D `Atomistic' Simulation Study / S. Saini -- A Full-Band Monte Carlo Model for Silicon Nanoscale Devices with a Quantum Mechanical Correction of the Potential / K. Hess -- Quantum Effects in MOSFETs: Use of an Effective Potential in 3D Monte Carlo Simulation of Ultra-Short Channel Devices / D. Vasileska -- Quantum Effects Along the Channel of Ultra-Scaled Si-Based MOSFETs? / S.
• Banerjee -- Session 13: Solid State Devices-Nanoelectronics / Atsushi Kurobe -- Single-Electron Pass-Transistor Logic: Operation of its Elemental Circuit / Y. Takahashi -- A Single-Electron Shut-Off Transistor for Scalable Sub-0.1-[MARC+6F]m Memory / K. Yano -- Engineering Variations: Towards Practical Single-Electron (Few-Electron) Memory / K. Yano -- Characteristics of P-Channel Si Nano-Crystal Memory / H. Shin -- Non-Volatile Si Quantum Memory with Self-Aligned Doubly-Stacked Dots / A. Toriumi -- A Novel FET-Type Ferroelectric Memory with Excellent Data Retention Characteristics / H.
• Ishiwara -- Session 14: CMOS and Interconnect Reliability-Reliability of Thin Oxides / Jordi Sune -- Substrate Enhanced Degradation of CMOS Devices / F. Piazza -- Degradation of Ultra-Thin Gate Oxides Accompanied by Hole Direct Tunneling: Can We Keep Long-Term Reliability of p-MOSFETs? / K. Taniguchi -- Experimental and Numerical Analysis of the Quantum Yield / G. Ghidini -- Anomalous Low Temperature Charge Leakage Mechanism in ULSI Flash Memories / T.-C. Chen -- Deuterium Effect on Interface States and SILC Generation in CHE Stress Conditions: A Comparative Study / L. Selmi -- Highly-reliable Gate Oxide under Fowler-Nordheim Electron Injection by Deuterium Pyrogenic Oxidation and Deuterated Poly-Si Deposition / A. Toriumi -- Session 15: Integrated Circuits and Manufacturing-Advanced DRAMs / Toshiba Werner -- An Orthogonal 6F2 Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM / G. Bronner -- Highly Manufacturable 4Gb DRAM Using 0.11[MARC+6F]m DRAM Technology / K.N. Kim -- Diagonal Layout & Surface Strap Trench (DST) cell / T. Hamamoto -- A Novel Bit-Line Process using Poly-Si Masked Dual-Damascene (PMDD) for 0.13[MARC+6F]m DRAMs and Beyond / Y. Kohyama -- A Fully Working 0.14[MARC+6F]m DRAM Technology with Polymetal (W/WNx/Poly-Si) Gate / S.-B. Han -- Novel Capacitor Technology for High Density Stand-Alone and Embedded DRAMs / M.Y. Lee -- Session 16: Quantum Electronics and Compound Semiconductors-GaN and RF Power Devices / Erhard Kohn.
• Explore the World of Microelectronics with the Proceedings of the 2000 IEEE International Electron Devices Meeting. IEDM is the leading forum for the presentation of research and development in the area of electron devices and their applications. Attended by the world's foremost experts in electron devices, this conference considers all the various types of electron devices available, including electron tubes, solid-state devices, and power devices. Also detailed are microelectronics, displays, sensors, processing, high voltage devices, and quantum and vacuum electronics.As previewed in the recent NY Times article "Exploring the Microelectronic World" http: /www.nytimes.com/2000/12/11/technology/11CHIP.html, the 2000 IEDM Conference presented a number of technical papers that explore the new ultra small world of microelectronics: "Single-Electron Pass-Transistor Logic: Operation of its Elemental Circuit"--NTT DoCoMo engineers describe transistors that can be switched on and off basedon the movement of a single electron."A Novel, Aerosol-Nanocrystal Floating-Gate Device for Non-Volatile Memory Applications"--Lucent Tech.
• English