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Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1523-1536

2022

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Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

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Hardware/Software Co-Exploration of Neural Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4805-4815

2020

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Specializing CGRAs for Light-Weight Convolutional Neural Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3387-3399

2022

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IEEE_Xplore

Improved Mapping of Quantum Circuits to IBM QX Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2375-2383

2020

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IEEE_Xplore

Exploring the Potential Benefits of Alternative Quantum Computing Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-09, Vol.40 (9), p.1825-1835

2021

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IEEE_Xplore

MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

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IEEE_Xplore

An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1226-1236

2019

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IEEE_Xplore

Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2109-2123

2020

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IEEE_Xplore

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951

2020

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IEEE_Xplore

FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-based In-memory Computing

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-09, Vol.42 (9), p.1-1

2023

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IEEE_Xplore

SCANN: Synthesis of Compact and Accurate Neural Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3012-3025

2022

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IEEE_Xplore

Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.2915-2928

2022

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Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1799-1812

2022

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IEEE_Xplore

Automatic Generation of Spatial Accelerator for Tensor Algebra

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-06, Vol.42 (6), p.1898-1911

2023

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Morphling: A Reconfigurable Architecture for Tensor Computation

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4733-4746

2022

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LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-06, Vol.42 (6), p.1784-1797

2023

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IEEE_Xplore

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3067-3080

2018

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IEEE_Xplore

SRNoC: An Ultra-Fast Configurable FPGA-Based NoC Simulator Using Switch-Router Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2798-2811

2020

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IEEE_Xplore

ReaDy: A ReRAM-based Processing-In-Memory Accelerator for Dynamic Graph Convolutional Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1

2022

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IEEE_Xplore

Programmable Crossbar Quantum-Dot Cellular Automata Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-08, Vol.36 (8), p.1367-1380

2017

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IEEE_Xplore

DLAU: A Scalable Deep Learning Accelerator Unit on FPGA

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-03, Vol.36 (3), p.513-517

2017

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IEEE_Xplore

ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-11, Vol.39 (11), p.3373-3384

2020

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IEEE_Xplore

From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1291-1304

2019

Link zum Volltext
IEEE_Xplore

McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-11, Vol.37 (11), p.2613-2622

2018

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IEEE_Xplore

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Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

Hardware/Software Co-Exploration of Neural Architectures

Specializing CGRAs for Light-Weight Convolutional Neural Networks

Improved Mapping of Quantum Circuits to IBM QX Architectures

Exploring the Potential Benefits of Alternative Quantum Computing Architectures

MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation

An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures

Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-based In-memory Computing

SCANN: Synthesis of Compact and Accurate Neural Networks

Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond

Automatic Generation of Spatial Accelerator for Tensor Algebra

Morphling: A Reconfigurable Architecture for Tensor Computation

LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

SRNoC: An Ultra-Fast Configurable FPGA-Based NoC Simulator Using Switch-Router Architecture

ReaDy: A ReRAM-based Processing-In-Memory Accelerator for Dynamic Graph Convolutional Networks

Programmable Crossbar Quantum-Dot Cellular Automata Circuits

DLAU: A Scalable Deep Learning Accelerator Unit on FPGA

ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture

From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration

McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM

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