UB Paderborn / Katalog / Suche / in CDI

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1523-1536

2022

Link zum Volltext

Verfügbarkeit prüfen

Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

Link zum Volltext

Verfügbarkeit prüfen

An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-07, Vol.38 (7), p.1226-1236

2019

Link zum Volltext
Volltext

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2938-2951

2020

Link zum Volltext
Volltext

Hardware/Software Co-Exploration of Neural Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4805-4815

2020

Link zum Volltext
Volltext

Specializing CGRAs for Light-Weight Convolutional Neural Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3387-3399

2022

Link zum Volltext
Volltext

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-10, Vol.34 (10), p.1537-1557

2015

Link zum Volltext
Volltext

MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-12, Vol.42 (12), p.1-1

2023

Link zum Volltext
Volltext

SCANN: Synthesis of Compact and Accurate Neural Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.3012-3025

2022

Link zum Volltext
Volltext

Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-09, Vol.41 (9), p.2915-2928

2022

Link zum Volltext

Verfügbarkeit prüfen

Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-11, Vol.42 (11), p.1-1

2023

Link zum Volltext
Volltext

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2434-2447

2020

Link zum Volltext

Verfügbarkeit prüfen

Improved Mapping of Quantum Circuits to IBM QX Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2375-2383

2020

Link zum Volltext
Volltext

Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-10, Vol.39 (10), p.2109-2123

2020

Link zum Volltext
Volltext

Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-06, Vol.41 (6), p.1799-1812

2022

Link zum Volltext
Volltext

On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1

2022

Link zum Volltext
Volltext

Exploring the Potential Benefits of Alternative Quantum Computing Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-09, Vol.40 (9), p.1825-1835

2021

Link zum Volltext
Volltext

CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.4975-4990

2022

Link zum Volltext
Volltext

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3067-3080

2018

Link zum Volltext
Volltext

ReaDy: A ReRAM-based Processing-In-Memory Accelerator for Dynamic Graph Convolutional Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-11, Vol.41 (11), p.1-1

2022

Link zum Volltext
Volltext

Programmable Crossbar Quantum-Dot Cellular Automata Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-08, Vol.36 (8), p.1367-1380

2017

Link zum Volltext
Volltext

DLAU: A Scalable Deep Learning Accelerator Unit on FPGA

IEEE transactions on computer-aided design of integrated circuits and systems, 2017-03, Vol.36 (3), p.513-517

2017

Link zum Volltext
Volltext

Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-11, Vol.38 (11), p.2072-2085

2019

Link zum Volltext
Volltext

Automatic Generation of Spatial Accelerator for Tensor Algebra

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-06, Vol.42 (6), p.1898-1911

2023

Link zum Volltext

Verfügbarkeit prüfen

Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-05, Vol.39 (5), p.1045-1058

2020

Link zum Volltext
Volltext

Menü

Weitere Dienste

Einstellungen

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

Gibbon: An Efficient Co-Exploration Framework of NN model and Processing-In-Memory Architecture

An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Hardware/Software Co-Exploration of Neural Architectures

Specializing CGRAs for Light-Weight Convolutional Neural Networks

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation

SCANN: Synthesis of Compact and Accurate Neural Networks

Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture

Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput

Improved Mapping of Quantum Circuits to IBM QX Architectures

Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures

Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond

On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures

Exploring the Potential Benefits of Alternative Quantum Computing Architectures

CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning

ReaDy: A ReRAM-based Processing-In-Memory Accelerator for Dynamic Graph Convolutional Networks

Programmable Crossbar Quantum-Dot Cellular Automata Circuits

DLAU: A Scalable Deep Learning Accelerator Unit on FPGA

Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks

Automatic Generation of Spatial Accelerator for Tensor Algebra

Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits

Aktive Filter

Suchergebnisse filtern