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Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

IEEE transactions on very large scale integration (VLSI) systems, 2013-06, Vol.21 (6), p.1094-1102

2013

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Recent progress in resistive random access memories: Materials, switching mechanisms, and performance

Materials science & engineering. R, Reports : a review journal, 2014-09, Vol.83, p.1-59

2014

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A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

IEEE journal of solid-state circuits, 2013-06, Vol.48 (6), p.1511-1520

2013

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Volltext

Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

IEEE transactions on very large scale integration (VLSI) systems, 2011-08, Vol.19 (8), p.1407-1417

2011

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Homogeneous barrier modulation of TaOx TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory

Nanotechnology, 2014-04, Vol.25 (16), p.165202-165202

2014

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Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

IEEE transactions on very large scale integration (VLSI) systems, 2010-01, Vol.18 (1), p.66-74

2010

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Resistive Switching by Voltage-Driven Ion Migration in Bipolar RRAM-Part II: Modeling

IEEE transactions on electron devices, 2012-09, Vol.59 (9), p.2468-2475

2012

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A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.869-879

2010

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Concurrent Average Memory Access Time

Computer (Long Beach, Calif.), 2014-05, Vol.47 (5), p.74-80

2014

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Volltext

Neural Modeling of Episodic Memory: Encoding, Retrieval, and Forgetting

IEEE transaction on neural networks and learning systems, 2012-10, Vol.23 (10), p.1574-1586

2012

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Cross-Point Memory Array Without Cell Selectors-Device Characteristics and Data Storage Pattern Dependencies

IEEE transactions on electron devices, 2010-10, Vol.57 (10), p.2531-2538

2010

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Volltext

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.109-120

2008

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Universal Reset Characteristics of Unipolar and Bipolar Metal-Oxide RRAM

IEEE transactions on electron devices, 2011-10, Vol.58 (10), p.3246-3253

2011

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Volltext

Flash memory cells-an overview

Proceedings of the IEEE, 1997-08, Vol.85 (8), p.1248-1271

1997

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Volltext

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.141-149

2008

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Volltext

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

IEEE journal of solid-state circuits, 2007-10, Vol.42 (10), p.2303-2313

2007

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Volltext

A Thermally Stable and High-Performance 90-nm Al2O3\Cu-Based 1T1R CBRAM Cell

IEEE transactions on electron devices, 2013-11, Vol.60 (11), p.3690-3695

2013

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Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective

IEEE transactions on very large scale integration (VLSI) systems, 2010-12, Vol.18 (12), p.1710-1723

2010

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Volltext

Modeling the Universal Set/Reset Characteristics of Bipolar RRAM by Field- and Temperature-Driven Filament Growth

IEEE transactions on electron devices, 2011-12, Vol.58 (12), p.4309-4317

Ielmini, D.

2011

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Volltext

Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems

IEEE transactions on very large scale integration (VLSI) systems, 2013-04, Vol.21 (4), p.706-719

2013

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Volltext

Codes for Asymmetric Limited-Magnitude Errors With Application to Multilevel Flash Memories

IEEE transactions on information theory, 2010-04, Vol.56 (4), p.1582-1595

2010

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Volltext

Nanoscale Bipolar and Complementary Resistive Switching Memory Based on Amorphous Carbon

IEEE transactions on electron devices, 2011-11, Vol.58 (11), p.3933-3939

2011

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Volltext

Filament Conduction and Reset Mechanism in NiO-Based Resistive-Switching Memory (RRAM) Devices

IEEE transactions on electron devices, 2009-02, Vol.56 (2), p.186-192

2009

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Phase-change memory: An architectural perspective

ACM computing surveys, 2013-06, Vol.45 (3), p.1-33

2013

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Set Variability and Failure Induced by Complementary Switching in Bipolar RRAM

IEEE electron device letters, 2013-07, Vol.34 (7), p.861-863

2013

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Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

Recent progress in resistive random access memories: Materials, switching mechanisms, and performance

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines

Homogeneous barrier modulation of TaOx TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory

Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed

Resistive Switching by Voltage-Driven Ion Migration in Bipolar RRAM-Part II: Modeling

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme

Concurrent Average Memory Access Time

Neural Modeling of Episodic Memory: Encoding, Retrieval, and Forgetting

Cross-Point Memory Array Without Cell Selectors-Device Characteristics and Data Storage Pattern Dependencies

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

Universal Reset Characteristics of Unipolar and Bipolar Metal-Oxide RRAM

Flash memory cells-an overview

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

A Thermally Stable and High-Performance 90-nm Al2O3\Cu-Based 1T1R CBRAM Cell

Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective

Modeling the Universal Set/Reset Characteristics of Bipolar RRAM by Field- and Temperature-Driven Filament Growth

Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems

Codes for Asymmetric Limited-Magnitude Errors With Application to Multilevel Flash Memories

Nanoscale Bipolar and Complementary Resistive Switching Memory Based on Amorphous Carbon

Filament Conduction and Reset Mechanism in NiO-Based Resistive-Switching Memory (RRAM) Devices

Phase-change memory: An architectural perspective

Set Variability and Failure Induced by Complementary Switching in Bipolar RRAM

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