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Application for CMP Technology on the Advanced ULSI Device Fabrication

Journal of the Japan Society for Precision Engineering, 2022/08/05, Vol.88(8), pp.627-630

2022

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Conference Report: The 32nd IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD 2020) September 13-18, 2020, Virtual

IEEJ Journal of Industry Applications, 2021-03, Vol.141 (3), p.NL3_2

真一郎, 林

2021

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Research Group Introduction: Gifu University, Faculty of Engineering, Department of Electrical, Electronic and Computer Engineering, Nakamura and Ito Laboratory

IEEJ Journal of Industry Applications, 2023-06, Vol.143 (6)

2023

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Techniques of BDD/ZDD: Brief History and Recent Activity

IEICE Transactions on Information and Systems, 2013/07/01, Vol.E96.D(7), pp.1419-1429

MINATO, Shin-ichi

2013

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Finite Virtual State Machines

IEICE Transactions on Information and Systems, 2012/10/01, Vol.E95.D(10), pp.2544-2547

2012

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Shape of Integrated System Interfacing between Cyber and Physical Space

IEICE ESS Fundamentals Review, 2023/01/01, Vol.16(3), pp.147-155

MIURA, Noriyuki

2023

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Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors

IEICE Transactions on Information and Systems, 2013/07/01, Vol.E96.D(7), pp.1443-1448

2013

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Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access

IEICE Transactions on Information and Systems, 2013/12/01, Vol.E96.D(12), pp.2765-2775

2013

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Development of a Robust and Compact On-Line Handwritten Japanese Text Recognizer for Hand-Held Devices

IEICE Transactions on Information and Systems, 2013/04/01, Vol.E96.D(4), pp.927-938

2013

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Round Addition Using Faults for Generalized Feistel Network

IEICE Transactions on Information and Systems, 2013/01/01, Vol.E96.D(1), pp.146-150

2013

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Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures

IEICE Transactions on Information and Systems, 2013/02/01, Vol.E96.D(2), pp.365-369

2013

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Region-Based Way-Partitioning on L1 Data Cache for Low Power

IEICE Transactions on Information and Systems, 2013/11/01, Vol.E96.D(11), pp.2466-2469

2013

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High Throughput Parallelization of AES-CTR Algorithm

IEICE Transactions on Information and Systems, 2013/08/01, Vol.E96.D(8), pp.1685-1695

2013

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On the Numbers of Products in Prefix SOPs for Interval Functions

IEICE Transactions on Information and Systems, 2013/05/01, Vol.E96.D(5), pp.1086-1094

2013

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Understanding the Impact of BPRAM on Incremental Checkpoint

IEICE Transactions on Information and Systems, 2013/03/01, Vol.E96.D(3), pp.663-672

2013

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An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors

IEICE Transactions on Information and Systems, 2012/11/01, Vol.E95.D(11), pp.2682-2692

2012

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Self-Organizing Incremental Associative Memory-Based Robot Navigation

IEICE Transactions on Information and Systems, 2012/10/01, Vol.E95.D(10), pp.2415-2425

2012

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Resco: Automatic Collection of Leaked Resources

IEICE Transactions on Information and Systems, 2013/01/01, Vol.E96.D(1), pp.28-39

2013

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Implementation and Optimization of Image Processing Algorithms on Embedded GPU

IEICE Transactions on Information and Systems, 2012/05/01, Vol.E95.D(5), pp.1475-1484

2012

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Adaptive Insertion and Promotion Policies Based on Least Recently Used Replacement

IEICE Transactions on Information and Systems, 2013/01/01, Vol.E96.D(1), pp.124-128

2013

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A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions

IEICE Transactions on Information and Systems, 2012/07/01, Vol.E95.D(7), pp.1847-1857

2012

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Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n-1, 2n+1-1} and {22n, 2n-1, 2n-1-1}

IEICE Transactions on Information and Systems, 2009/09/01, Vol.E92.D(9), pp.1628-1638

2009

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Reconfigurable Multi-Resolution Performance Profiling in Android Applications

IEICE Transactions on Information and Systems, 2013/09/01, Vol.E96.D(9), pp.2039-2046

2013

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Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA

IEICE Transactions on Information and Systems, 2012/10/01, Vol.E95.D(10), pp.2369-2376

2012

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Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

IEICE Transactions on Information and Systems, 2012/07/01, Vol.E95.D(7), pp.1858-1871

2012

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Application for CMP Technology on the Advanced ULSI Device Fabrication

Conference Report: The 32nd IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD 2020) September 13-18, 2020, Virtual

Research Group Introduction: Gifu University, Faculty of Engineering, Department of Electrical, Electronic and Computer Engineering, Nakamura and Ito Laboratory

Techniques of BDD/ZDD: Brief History and Recent Activity

Finite Virtual State Machines

Shape of Integrated System Interfacing between Cyber and Physical Space

Effective Fixed-Point Pipelined Divider for Mobile Rendering Processors

Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access

Development of a Robust and Compact On-Line Handwritten Japanese Text Recognizer for Hand-Held Devices

Round Addition Using Faults for Generalized Feistel Network

Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures

Region-Based Way-Partitioning on L1 Data Cache for Low Power

High Throughput Parallelization of AES-CTR Algorithm

On the Numbers of Products in Prefix SOPs for Interval Functions

Understanding the Impact of BPRAM on Incremental Checkpoint

An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors

Self-Organizing Incremental Associative Memory-Based Robot Navigation

Resco: Automatic Collection of Leaked Resources

Implementation and Optimization of Image Processing Algorithms on Embedded GPU

Adaptive Insertion and Promotion Policies Based on Least Recently Used Replacement

A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions

Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n-1, 2n+1-1} and {22n, 2n-1, 2n-1-1}

Reconfigurable Multi-Resolution Performance Profiling in Android Applications

Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

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