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The (001) surface and morphology of thin Fe3O4 layers grown by O2-assisted molecular beam epitaxy

Surface science, 2001-07, Vol.486 (1-2), p.73-81

2001

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The 0 ∕ 0 problem in the Fuzzy-Logical Model of Perception

The Journal of the Acoustical Society of America, 2006-10, Vol.120 (4), p.1795-1798

Schwartz, Jean-Luc

2006

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0/0 Simplifies implicitization

Journal of symbolic computation, 2008-06, Vol.43 (6), p.475-489

Chionh, Eng-Wee

2008

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A 0.0012 mm[sup.2] 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

Electronics (Basel), 2022-06, Vol.11 (11)

2022

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A 0.0018 mm frequency-to-digital-converter-based CMOS smart temperature sensor

Analog integrated circuits and signal processing, 2010-08, Vol.64 (2), p.153-157

2010

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A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

Integration (Amsterdam), 2021-05, Vol.78, p.135-143

2021

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A 0.00426 mm[sup.2] 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

Electronics (Basel), 2022-11, Vol.11 (21)

2022

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A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R- RC Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1248

2023

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0.01 Cent per Second: Developing a Cloud-based Cost-effective Audio Transcription System for an Online Video Learning Platform

2023 20th International Joint Conference on Computer Science and Software Engineering (JCSSE), 2023, p.432-437

2023

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A 0.01-degree gridded precipitation dataset for Japan, 1926-2020

Scientific data, 2022-07, Vol.9 (1), p.422-422, Article 422

2022

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A 0.01%THD, 70dB PSRR Single Ended Class D using variable hysteresis control for headphone amplifiers

2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, p.1181-1184

2009

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A 0.016 mV/mA Cross-Regulation 5-Output SIMO DC-DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme

IEEE transactions on power electronics, 2018-11, Vol.33 (11), p.9619-9630

2018

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A 0.025% DC Current Mismatch Charge Pump for PLL Applications

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, p.700-703

2021

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A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit

2020 IEEE Symposium on VLSI Circuits, 2020, p.1-2

2020

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A 0.084 nJ/b FSK transmitter and 4.8 μW OOK receiver for ISM-band medical sensor networks

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013, p.1-4

2013

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A 0.1-13 GHz Wide Range Multi-Modulus Divider with Adaptive Sensitivity for Broad Band Operation

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS), 2018, p.901-904

2018

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{O, 1/2}-Chvátal-Gomory cuts

Mathematical programming, 1996-09, Vol.74 (3), p.221-235

1996

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A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2017-03, Vol.25 (3), p.1044-1053

2017

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0, 1, 2, many - A classroom occupancy monitoring system for smart public buildings

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014, p.1-6

2014

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A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2016-05, Vol.24 (5), p.1975-1983

2016

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A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

Analog integrated circuits and signal processing, 2013-12, Vol.77 (3), p.567-582

2013

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A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2015-05, Vol.23 (5), p.944-957

2015

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A 0.1-9-GHz Frequency Synthesizer for Avionic SDR Applications in 0.13-μm CMOS Technology

IEEE transactions on very large scale integration (VLSI) systems, 2021-12, Vol.29 (12), p.2119-2129

2021

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0/1/All CSPs, Half-Integral A-Path Packing, and Linear-Time FPT Algorithms

2018 IEEE 59th Annual Symposium on Foundations of Computer Science (FOCS), 2018, p.462-473

2018

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0-1 Combinatorial Optimization Problems with Qualitative and Uncertain Profits

Integrated Uncertainty in Knowledge Modelling and Decision Making, 2023, Vol.14375, p.139-151

2023

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The (001) surface and morphology of thin Fe3O4 layers grown by O2-assisted molecular beam epitaxy

The 0 ∕ 0 problem in the Fuzzy-Logical Model of Perception

0/0 Simplifies implicitization

A 0.0012 mm[sup.2] 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

A 0.0018 mm frequency-to-digital-converter-based CMOS smart temperature sensor

A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

A 0.00426 mm[sup.2] 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R- RC Network

0.01 Cent per Second: Developing a Cloud-based Cost-effective Audio Transcription System for an Online Video Learning Platform

A 0.01-degree gridded precipitation dataset for Japan, 1926-2020

A 0.01%THD, 70dB PSRR Single Ended Class D using variable hysteresis control for headphone amplifiers

A 0.016 mV/mA Cross-Regulation 5-Output SIMO DC-DC Buck Converter Using Output-Voltage-Aware Charge Control Scheme

A 0.025% DC Current Mismatch Charge Pump for PLL Applications

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit

A 0.084 nJ/b FSK transmitter and 4.8 μW OOK receiver for ISM-band medical sensor networks

A 0.1-13 GHz Wide Range Multi-Modulus Divider with Adaptive Sensitivity for Broad Band Operation

{O, 1/2}-Chvátal-Gomory cuts

A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

0, 1, 2, many - A classroom occupancy monitoring system for smart public buildings

A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

A 0.1-9-GHz Frequency Synthesizer for Avionic SDR Applications in 0.13-μm CMOS Technology

0/1/All CSPs, Half-Integral A-Path Packing, and Linear-Time FPT Algorithms

0-1 Combinatorial Optimization Problems with Qualitative and Uncertain Profits

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