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Three-Dimensional Integrated Circuit Design
Second edition, 2017
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Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack
IEEE transactions on computer-aided design of integrated circuits and systems, 2020-08, Vol.39 (8), p.1607-1620
2020
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Synthesis of Hidden State Transitions for Sequential Logic Locking
IEEE transactions on computer-aided design of integrated circuits and systems, 2021-01, Vol.40 (1), p.11-23
2021
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Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking
IEEE transactions on computer-aided design of integrated circuits and systems, 2021-01, Vol.40 (1), p.38-51
2021
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On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors
IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2230-2240
2018
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Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5
2023
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A Power Side-Channel Attack on Flash ADC
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5
2023
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Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5
2023
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Reconfigurable Array for Analog Applications
2021 IEEE 39th International Conference on Computer Design (ICCD), 2021, p.361-365
2021
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Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery
IEEE transactions on very large scale integration (VLSI) systems, 2017-09, Vol.25 (9), p.2538-2551
2017
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Applying Swarm Intelligence to Distributed On-Chip Power Management
2019 IEEE 37th International Conference on Computer Design (ICCD), 2019, p.532-540
2019
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Hidden Costs of Analog Deobfuscation Attacks
IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1802-1815
2023
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An intra-chip free-space optical interconnect
Proceedings of the 37th annual international symposium on computer architecture, 2010, p.94-105
2010
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Performance and Security Analysis of Parameter-Obfuscated Analog Circuits
IEEE transactions on very large scale integration (VLSI) systems, 2021-12, Vol.29 (12), p.2013-2026
2021
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Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits
IEEE transactions on very large scale integration (VLSI) systems, 2015-10, Vol.23 (10), p.2077-2089
2015
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ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling
IEEE transactions on very large scale integration (VLSI) systems, 2018-02, Vol.26 (2), p.249-261
2018
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Robust Low Power Clock Synchronization for Multi-Die Systems
2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2019, p.1-6
2019
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Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich Architectures
2018 IEEE 36th International Conference on Computer Design (ICCD), 2018, p.83-91
2018
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Clock Distribution Networks in 3-D Integrated Systems
IEEE transactions on very large scale integration (VLSI) systems, 2011-12, Vol.19 (12), p.2256-2266
2011
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Corruptibility Profile of Logic Locked Circuits for SAT Attacks with Execution Time Budgets
2022 IEEE 15th Dallas Circuit And System Conference (DCAS), 2022, p.1-5
2022
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Variation-aware Analog Circuit Sizing with Classifier Chains
2021 ACM/IEEE 3rd Workshop on Machine Learning for CAD (MLCAD), 2021, p.1-6
2021
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CALT: Classification with Adaptive Labeling Thresholds for Analog Circuit Sizing
2020 ACM/IEEE 2nd Workshop on Machine Learning for CAD (MLCAD), 2020, p.49-54
2020
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Editorial TVLSI Positioning-Continuing and Accelerating an Upward Trajectory
IEEE transactions on very large scale integration (VLSI) systems, 2019-02, Vol.27 (2), p.253-280
2019
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Electrical modeling and characterization of 3-D vias
2008 IEEE International Symposium on Circuits and Systems, 2008, p.784-787
2008
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Evolving On-Chip Power Delivery through Particle Swarm Optimization
2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD), 2019, p.1-6
2019
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