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Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack
IEEE transactions on computer-aided design of integrated circuits and systems, 2020-08, Vol.39 (8), p.1607-1620
2020
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Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance
IEEE transactions on electron devices, 2009-09, Vol.56 (9), p.1873-1881
2009
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Synthesis of Hidden State Transitions for Sequential Logic Locking
IEEE transactions on computer-aided design of integrated circuits and systems, 2021-01, Vol.40 (1), p.11-23
2021
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Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking
IEEE transactions on computer-aided design of integrated circuits and systems, 2021-01, Vol.40 (1), p.38-51
2021
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Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits
Microelectronics, 2010, Vol.41 (1), p.9-16
2010
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On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors
IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2230-2240
2018
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Circuit-GNN: A Graph Neural Network for Transistor-level Modeling of Analog Circuit Hierarchies
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5
2023
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A Power Side-Channel Attack on Flash ADC
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5
2023
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Graph Representation Learning for Parasitic Impedance Prediction of the Interconnect
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 2023, p.1-5
2023
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Transfer Learning for Reuse of Analog Circuit Sizing Models Across Technology Nodes
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.1033-1037
2022
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Reconfigurable Analog Array for Hardware Security
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.1047-1051
2022
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Reconfigurable Array for Analog Applications
2021 IEEE 39th International Conference on Computer Design (ICCD), 2021, p.361-365
2021
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Synthesis of Coupling Capacitance Based Hidden State Transitions for Sequential Logic Locking
2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, p.1734-1738
2022
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A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips
IEEE photonics technology letters, 2011-02, Vol.23 (3), p.164-166
2011
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Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators
IEEE journal on emerging and selected topics in circuits and systems, 2021-12, Vol.11 (4), p.762-775
2021
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Increasing the SAT Attack Resiliency of In-Cone Logic Locking
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5
2019
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Reducing Logic Locking Key Leakage through the Scan Chain
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5
2020
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Dynamic differential signaling based logic families for robust ultra-low power near-threshold computing
Microelectronics, 2020-08, Vol.102, p.104801, Article 104801
2020
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Mesh Based Obfuscation of Analog Circuit Properties
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5
2019
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Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery
IEEE transactions on very large scale integration (VLSI) systems, 2017-09, Vol.25 (9), p.2538-2551
2017
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Applying Swarm Intelligence to Distributed On-Chip Power Management
2019 IEEE 37th International Conference on Computer Design (ICCD), 2019, p.532-540
2019
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Hidden Costs of Analog Deobfuscation Attacks
IEEE transactions on very large scale integration (VLSI) systems, 2023-11, Vol.31 (11), p.1802-1815
2023
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An intra-chip free-space optical interconnect
Proceedings of the 37th annual international symposium on computer architecture, 2010, p.94-105
2010
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Performance and Security Analysis of Parameter-Obfuscated Analog Circuits
IEEE transactions on very large scale integration (VLSI) systems, 2021-12, Vol.29 (12), p.2013-2026
2021
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Modeling SAT-Attack Search Complexity
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5
2020
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