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A High Dynamic-Range Neural Recording Chopper Amplifier for Simultaneous Neural Recording and Stimulation
IEEE journal of solid-state circuits, 2017-03, Vol.52 (3), p.645-656
2017
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A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction
IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.173-184
2017
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A 130- \mu W, 64-Channel Neural Spike-Sorting DSP Chip
IEEE journal of solid-state circuits, 2011-05, Vol.46 (5), p.1214-1222
2011
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Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example
IEEE journal of solid-state circuits, 2012-03, Vol.47 (3), p.757-768
2012
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Analysis and Design of a Robust, Low-Power, Inductively Coupled LSK Data Link
IEEE journal of solid-state circuits, 2020-09, Vol.55 (9), p.2583-2596
2020
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A Configurable 12-237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals
IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.68-78
2016
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Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications
IEEE journal of solid-state circuits, 2011-01, Vol.46 (1), p.308-320
2011
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A 15.2-ENOB 5-kHz BW 4.5- \mu W Chopped CT \Delta\Sigma -ADC for Artifact-Tolerant Neural Recording Front Ends
IEEE journal of solid-state circuits, 2018-12, Vol.53 (12), p.3470-3483
2018
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An 80-mVpp Linear-Input Range, 1.6-GΩ Input Impedance, Low-Power Chopper Amplifier for Closed-Loop Neural Recording That Is Tolerant to 650-mVpp Common-Mode Interference
IEEE journal of solid-state circuits, 2017-11, p.1-18
2017
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A Multi-Granularity FPGA With Hierarchical Interconnects for Efficient and Flexible Mobile Computing
IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.137-149
2015
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Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference
IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.3-7
2017
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A 2.267-Gb/s, 93.7-pJ/bit Non-Binary LDPC Decoder With Logarithmic Quantization and Dual-Decoding Algorithm Scheme for Storage Applications
IEEE journal of solid-state circuits, 2018-08, Vol.53 (8), p.2378-2388
2018
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A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios
IEEE journal of solid-state circuits, 2012-09, Vol.47 (9), p.2235-2245
2012
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A 75-μW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering
IEEE journal of solid-state circuits, 2013-09, Vol.48 (9), p.2230-2238
2013
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A 15.2-ENOB 5-kHz BW 4.5-[Formula Omitted]W Chopped CT [Formula Omitted]-ADC for Artifact-Tolerant Neural Recording Front Ends
IEEE journal of solid-state circuits, 2018-01, Vol.53 (12), p.3470
2018
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An 80-mVpp Linear-Input Range, 1.6- \text\Omega Input Impedance, Low-Power Chopper Amplifier for Closed-Loop Neural Recording That Is Tolerant to 650-mVpp Common-Mode Interference
IEEE journal of solid-state circuits, 2017-11, Vol.52 (11), p.2811-2828
2017
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Power and Area Minimization for Multidimensional Signal Processing
IEEE journal of solid-state circuits, 2007-04, Vol.42 (4), p.922-934
2007
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Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils
IEEE journal of solid-state circuits, 2019-04, Vol.54 (4), p.1003-1016
2019
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A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration
IEEE journal of solid-state circuits, 2023-01, Vol.58 (1), p.111-123
2023
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A design environment for high-throughput low-power dedicated signal processing systems
IEEE journal of solid-state circuits, 2002-03, Vol.37 (3), p.420-431
2002
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A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering
IEEE journal of solid-state circuits, 2013-09, Vol.48 (9), p.2230-2238
2013
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A 130-[Formula Omitted]W, 64-Channel Neural Spike-Sorting DSP Chip
IEEE journal of solid-state circuits, 2011-05, Vol.46 (5), p.1214
2011
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Methods for true energy-performance optimization
IEEE journal of solid-state circuits, 2004-08, Vol.39 (8), p.1282-1293
2004
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