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Selected Topics in RF, Analog and Mixed Signal Circuits and Systems

1, 2017

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Trellis-Based Extended Min-Sum Algorithm for Non-Binary LDPC Codes and its Hardware Structure

IEEE transactions on communications, 2013-07, Vol.61 (7), p.2600-2611

2013

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Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels

2009 22nd International Conference on VLSI Design, 2009, p.51-56

2009

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An efficient reconfigurable hardware accelerator for convolutional neural networks

2017 51st Asilomar Conference on Signals, Systems, and Computers, 2017, p.1337-1341

2017

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Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes"

EURASIP journal on embedded systems, 2009-01, Vol.2009 (1), p.704174

2009

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Vision-Based Sensor and Navigation System for Autonomous Air Refueling

Journal of guidance, control, and dynamics, 2005-09, Vol.28 (5), p.979-989

2005

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A vision-based DSP embedded navigation sensor

IEEE sensors journal, 2002-10, Vol.2 (5), p.428-442

2002

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Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.1645-1648

2007

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Volltext

Low latency T-EMS decoder for non-binary LDPC codes

2013 Asilomar Conference on Signals, Systems and Computers, 2013, p.831-835

2013

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IEEE CONECCT? 2014 a Success for the IEEE Bangalore Section [Chapters]

IEEE solid state circuits magazine, 2014, Vol.6 (2), p.90-91

Gunnam, Kiran

2014

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A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007, p.738-743

2007

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DL Vojin G. Oklobdzija Presents a "Methodology for the Energy-Efficient Design of Digital Circuits" at SSCS-Santa Clara Valley [People]

IEEE solid state circuits magazine, 2010-07, Vol.2 (3), p.63

Gunnam, Kiran

2010

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Sanchez-Sinencio Gives Invited Talk on Low Drop-Out Linear Regulators at SSCS-Santa Clara Valley [Chapters]

IEEE solid state circuits magazine, 2010-04, Vol.2 (2), p.60

Gunnam, Kiran

2010

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Sanchez-Sinencio Gives Invited Talk on Low Drop-Out Linear Regulators at SSCS-Santa Clara Valley [Chapters

IEEE solid state circuits magazine, 2010, Vol.2 (2), p.60-61

Gunnam, Kiran

2010

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DL Vojin G. Oklobdzija Presents a “Methodology for the Energy-Efficient Design of Digital Circuits” at SSCS-Santa Clara Valley [People

IEEE solid state circuits magazine, 2010, Vol.2 (3), p.63-65

Gunnam, Kiran

2010

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Next generation iterative LDPC solutions for magnetic recording storage

2008 42nd Asilomar Conference on Signals, Systems and Computers, 2008, p.1148-1152

2008

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Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation

2006 Fortieth Asilomar Conference on Signals, Systems and Computers, 2006, p.1192-1199

2006

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Volltext

Phase Lock Loop Design Techniques

Selected Topics in RF, Analog and Mixed Signal Circuits and Systems, 2017, p.71-93

1, 2017

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Equalization and A/D Conversion for High-Speed Links

Selected Topics in RF, Analog and Mixed Signal Circuits and Systems, 2017, p.147-191

1, 2017

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Introduction

Selected Topics in RF, Analog and Mixed Signal Circuits and Systems, 2017, p.7-8

1, 2017

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Clock and Timing in Wireline Communications

Selected Topics in RF, Analog and Mixed Signal Circuits and Systems, 2017, p.41-69

1, 2017

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Linearity, Time-Variation, Phase Modulation and Oscillator Phase Noise

Selected Topics in RF, Analog and Mixed Signal Circuits and Systems, 2017, p.9-39

1, 2017

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mm-Wave and Terahertz Signal Generation, Synthesis and Amplification: Reaching the Fundamental Limits

Selected Topics in RF, Analog and Mixed Signal Circuits and Systems, 2017, p.95-146

1, 2017

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Algorithms and vlsi architectures for low-density parity-check codes: part 2 - efficient coding architectures

IEEE solid state circuits magazine, 2017-01, Vol.9 (1), p.23-28

2017

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Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation

Gunnam, Kiran Kumar

2006

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Selected Topics in RF, Analog and Mixed Signal Circuits and Systems

Trellis-Based Extended Min-Sum Algorithm for Non-Binary LDPC Codes and its Hardware Structure

Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels

An efficient reconfigurable hardware accelerator for convolutional neural networks

Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes"

Vision-Based Sensor and Navigation System for Autonomous Air Refueling

A vision-based DSP embedded navigation sensor

Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

Low latency T-EMS decoder for non-binary LDPC codes

IEEE CONECCT? 2014 a Success for the IEEE Bangalore Section [Chapters]

A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes

DL Vojin G. Oklobdzija Presents a "Methodology for the Energy-Efficient Design of Digital Circuits" at SSCS-Santa Clara Valley [People]

Sanchez-Sinencio Gives Invited Talk on Low Drop-Out Linear Regulators at SSCS-Santa Clara Valley [Chapters]

Sanchez-Sinencio Gives Invited Talk on Low Drop-Out Linear Regulators at SSCS-Santa Clara Valley [Chapters

DL Vojin G. Oklobdzija Presents a “Methodology for the Energy-Efficient Design of Digital Circuits” at SSCS-Santa Clara Valley [People

Next generation iterative LDPC solutions for magnetic recording storage

Decoding of Quasi-cyclic LDPC Codes Using an On-the-Fly Computation

Phase Lock Loop Design Techniques

Equalization and A/D Conversion for High-Speed Links

Introduction

Clock and Timing in Wireline Communications

Linearity, Time-Variation, Phase Modulation and Oscillator Phase Noise

mm-Wave and Terahertz Signal Generation, Synthesis and Amplification: Reaching the Fundamental Limits

Algorithms and vlsi architectures for low-density parity-check codes: part 2 - efficient coding architectures

Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation

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