UB Paderborn / Katalog / Suche / in CDI

0.(Brief article)

State legislatures, 2014-06, Vol.40 (6), p.4

2014

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A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

Electronics (Basel), 2022-05, Vol.11 (11), p.1707

2022

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A 0.0016 mm² 0.64 nJ leakage-based CMOS temperature sensor

Sensors (Basel, Switzerland), 2013-09, Vol.13 (9), p.12648-12662

2013

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A 0.004-mm ^ Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

IEEE transactions on circuits and systems. II, Express briefs, 2008-02, Vol.55 (2), p.116-120

2008

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Volltext

A 0.004-mm super(2) Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

IEEE transactions on circuits and systems. II, Express briefs, 2008-01, Vol.55 (2)

2008

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A 0.004-mm2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

IEEE transactions on circuits and systems. II, Express briefs, 2008-02, Vol.55 (2), p.116

2008

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A 0.00426 mm2 77.6-dB Dynamic Range VCO-Based CTDSM for Multi-Channel Neural Recording

Electronics (Basel), 2022-10, Vol.11 (21), p.3477

2022

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A 0.0043-mm ^ 0.085- \mu W/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-02, p.1-5

2023

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Volltext

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R- RC Network

IEEE transactions on very large scale integration (VLSI) systems, 2023-08, Vol.31 (8), p.1248

2023

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A 0.0045- [Formula Omitted] 32.4- [Formula Omitted] Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2015-03, Vol.62 (3), p.246

2015

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A 0.0045- \hbox^ 32.4- \mu\hbox Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2015-03, Vol.62 (3), p.246-250

2015

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Volltext

A 0.0045- $\hbox{mm}2}$ 32.4- $\mu\hbox{W} $ Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

IEEE transactions on circuits and systems. II, Express briefs, 2015-03, Vol.62 (3), p.246-250

2015

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A 0.0054-mm 2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor

IEEE transactions on circuits and systems. II, Express briefs, 2016-05, Vol.63 (5), p.413-417

2016

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A 0.0054-mm super(2) Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor

IEEE transactions on circuits and systems. II, Express briefs, 2016-05, Vol.63 (5), p.413-417

2016

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A 0.0054-mm2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor

IEEE transactions on circuits and systems. II, Express briefs, 2016-05, Vol.63 (5), p.413-417

2016

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Volltext

A 0.007 mm 2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-09, Vol.68 (9), p.3088-3092

2021

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A 0.007 mm2 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2021-09, Vol.68 (9), p.3088-3092

2021

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Volltext

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

International journal of circuit theory and applications, 2017-04, Vol.45 (4), p.466-482

2017

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A 0.009-1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

IEEE transactions on circuits and systems. II, Express briefs, 2015-12, Vol.62 (12), p.1129-1133

2015

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Volltext

0.009856 m3: Between the Book, the Model, and the Built in the Vedute Collection of Three-Dimensional Manuscripts

Architecture and culture, 2016-03, Vol.4 (1), p.31-50

Macken, Marian

2016

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A 0.011%/V LS and −76-dB PSRR Self-Biased CMOS Voltage Reference With Quasi Self-Cascode Current Mirror

IEEE transactions on circuits and systems. II, Express briefs, 2024-03, Vol.71 (3), p.1052

2024

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A 0.011%/V LS and -76dB PSRR Self-Biased CMOS Voltage Reference with Quasi Self-Cascode Current Mirror

IEEE transactions on circuits and systems. II, Express briefs, 2023-09, p.1-1

2023

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Volltext

A 0.0129 mm 2 DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2018-12, Vol.65 (12), p.1844-1848

2018

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A 0.0129 mm2 DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2018-12, Vol.65 (12), p.1844-1848

2018

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Volltext

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