UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Leakier Wires: Exploiting FPGA Long Wires for Covert- and Side-channel Attacks

ACM transactions on reconfigurable technology and systems, 2019-09, Vol.12 (3), p.1-29

2019

Volltextzugriff (PDF)

A Novel Delay Calibration Method Considering Interaction between Cells and Wires

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, p.1-6

2023

Volltextzugriff (PDF)

3D layout of the Spidergon-Donut on-chip interconnection network

International journal of high performance systems architecture, 2023, Vol.11 (3), p.137

2023

Volltextzugriff (PDF)

Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions

Technical review - IETE, 2019-11, Vol.36 (6), p.580-593

2019

Volltextzugriff (PDF)

Thermal Aware Floor planning Technique for Nano Circuits

Research Journal of Applied Sciences, Engineering and Technology, 2014-09, Vol.8 (10), p.1279-1284

2014

Volltextzugriff (PDF)

Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches

IEEE transactions on very large scale integration (VLSI) systems, 2014-01, Vol.22 (1), p.185-190

2014

Volltextzugriff (PDF)

A workload independent energy reduction strategy for D-NUCA caches

The Journal of supercomputing, 2014-04, Vol.68 (1), p.157-182

2014

Volltextzugriff (PDF)

Thermal aware floorplanning incorporating temperature dependent wire delay estimation

Microprocessors and microsystems, 2015-11, Vol.39 (8), p.807-815

2015

Volltextzugriff (PDF)

Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

Applied mathematics & information sciences, 2014-09, Vol.8 (5), p.2277-2285

2014

Volltextzugriff (PDF)

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

Electronics (Basel), 2017-12, Vol.6 (4), p.78

2017

Volltextzugriff (PDF)

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

IEEE transactions on very large scale integration (VLSI) systems, 2008-04, Vol.16 (4), p.456-465

2008

Volltextzugriff (PDF)

Signal Transition Graphs for Asynchronous Data Path Circuits

Modelirovanie i analiz informacionnyh sistem, 2023-06, Vol.30 (2), p.170-186

2023

Volltextzugriff (PDF)

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2011, Vol.E94-A (12), p.2619-2627

2011

Volltextzugriff (PDF)

Leaky Wires: Information Leakage and Covert Communication Between FPGA Long Wires

Proceedings of the 2018 on Asia Conference on Computer and Communications Security, 2018, p.15-27

2018

Volltextzugriff (PDF)

Introduction

Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling, 2020, p.1-16

2020

Volltextzugriff (PDF)

Analysis of Performance Dependencies in NUCA-Based CMP Systems

2009 21st International Symposium on Computer Architecture and High Performance Computing, 2009, p.49-56

2009

Volltextzugriff (PDF)

Analysis of static and dynamic energy consumption in NUCA caches: initial results

Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture, 2007, p.105-112

2007

Volltextzugriff (PDF)

A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay

2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS), 2021, p.1-6

2021

Volltextzugriff (PDF)

Designing fast on-chip interconnects for deep submicrometer technologies

IEEE transactions on very large scale integration (VLSI) systems, 2003-04, Vol.11 (2), p.276-280

2003

Volltextzugriff (PDF)

Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture

Embedded and Ubiquitous Computing – EUC 2005, 2005, p.448-457

2005

Volltextzugriff (PDF)

Single FU Bypass Networks for High Clock Rate Superscalar Processors

High Performance Computing - HiPC 2004, 2004, p.319-332

2004

Volltextzugriff (PDF)

A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor

Microprocessors and microsystems, 2007-03, Vol.31 (2), p.146-159

2007

Volltextzugriff (PDF)

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015, p.1-8

2015

Volltextzugriff (PDF)

Energy Behaviour of NUCA Caches in CMPs

2011 14th Euromicro Conference on Digital System Design, 2011, p.746-753

2011

Volltextzugriff (PDF)

Reconfigurable Clock Networks, Automated Design Flows, Run-Time Optimization, and Case Study

Adaptive Digital Circuits for Power-Performance Range Beyond Wide Voltage Scaling, 2020, p.115-144

2020

Volltextzugriff (PDF)

1 – 25 von 3.922

Menü

Weitere Dienste

Einstellungen

Leakier Wires: Exploiting FPGA Long Wires for Covert- and Side-channel Attacks

A Novel Delay Calibration Method Considering Interaction between Cells and Wires

3D layout of the Spidergon-Donut on-chip interconnection network

Timing Closure Problem: Review of Challenges at Advanced Process Nodes and Solutions

Thermal Aware Floor planning Technique for Nano Circuits

Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches

A workload independent energy reduction strategy for D-NUCA caches

Thermal aware floorplanning incorporating temperature dependent wire delay estimation

Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

Signal Transition Graphs for Asynchronous Data Path Circuits

Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor

Leaky Wires: Information Leakage and Covert Communication Between FPGA Long Wires

Introduction

Analysis of Performance Dependencies in NUCA-Based CMP Systems

Analysis of static and dynamic energy consumption in NUCA caches: initial results

A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay

Designing fast on-chip interconnects for deep submicrometer technologies

Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture

Single FU Bypass Networks for High Clock Rate Superscalar Processors

A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck

Energy Behaviour of NUCA Caches in CMPs

Reconfigurable Clock Networks, Automated Design Flows, Run-Time Optimization, and Case Study

Suchergebnisse filtern