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A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

IEEE transactions on emerging topics in computing, 2019-07, Vol.7 (3), p.447-455

2019

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A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

IEEE journal of solid-state circuits, 2007-04, Vol.42 (4), p.820-829

2007

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A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

IEEE journal of solid-state circuits, 2008-09, Vol.43 (9), p.2109-2119

2008

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A 0.41 μA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.917-923

2013

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A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018, p.266-270

2018

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Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

IEEE journal of solid-state circuits, 2009-03, Vol.44 (3), p.977-986

2009

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A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

IEEE journal of solid-state circuits, 2013-04, Vol.48 (4), p.917-923

2013

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A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2535-2544

2011

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A Precise Implementation of Random Access Time Measurement for Embedded SRAM

Journal of the Institution of Engineers (India). Series B, Electrical Engineering, Electronics and telecommunication engineering, Computer engineering, 2019-10, Vol.100 (5), p.525-528

2019

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A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

IEEE journal of solid-state circuits, 2004-04, Vol.39 (4), p.684-693

2004

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Predictable Power Saving Memory Controller Circuit Design for Embedded Static Random Access Memory

IEEE transactions on magnetics, 2014-07, Vol.50 (7), p.1-5

2014

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Design of 8T ROM embedded SRAM using double wordline for low power high speed application

2016 International Conference on Communication and Signal Processing (ICCSP), 2016, p.0921-0925

2016

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Area efficient diode and on transistor inter-changeable power gating scheme with trim options for SRAM design in nano-complementary metal oxide semiconductor technology

IET circuits, devices & systems, 2014-03, Vol.8 (2), p.100-106

2014

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A write buffer design based on stable and area-saving embedded SRAM for flash applications

Science China. Technological sciences, 2015-02, Vol.58 (2), p.357-361

2015

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A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.96-108

2008

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Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems

IEEE transactions on very large scale integration (VLSI) systems, 2013-07, Vol.21 (7), p.1299-1307

2013

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An Area Efficient Built-In Redundancy Analysis for Embedded Memory with Selectable 1-D Redundancy

Intelligent Systems Technologies and Applications 2016, p.721-728

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AN EFFECTIVE TEST ALGORITHM AND DIAGNOSTIC IMPLEMENTATION FOR EMBEDDED STATIC RANDOM ACCESS MEMORIES

Journal of circuits, systems, and computers, 2011-11, Vol.20 (7), p.1389-1402

2011

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Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM

2012 25th International Conference on VLSI Design, 2012, p.412-417

Srinivasaiah, H. C.

2012

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A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.152-160

2006

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Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs

IEEE transactions on very large scale integration (VLSI) systems, 2005-10, Vol.13 (10), p.1127-1135

2005

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Reduction of Area per Good Die for SoC Memory Built-In Self-Test

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2010, Vol.E93-A (12), p.2463-2471

2010

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GuardiaNN: Fast and Secure On-Device Inference in TrustZone Using Embedded SRAM and Cryptographic Hardware

Proceedings of the 23rd ACM/IFIP International Middleware Conference, 2022, p.15-28

2022

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Area Efficient ROM-Embedded SRAM Cache

IEEE transactions on very large scale integration (VLSI) systems, 2013-09, Vol.21 (9), p.1583-1595

2013

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Power Characterization of Embedded SRAMs for Power Binning

2012 IEEE 30th VLSI Test Symposium (VTS), 2012, p.203-208

2012

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A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

A 0.41 μA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

A Precise Implementation of Random Access Time Measurement for Embedded SRAM

A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications

Predictable Power Saving Memory Controller Circuit Design for Embedded Static Random Access Memory

Design of 8T ROM embedded SRAM using double wordline for low power high speed application

Area efficient diode and on transistor inter-changeable power gating scheme with trim options for SRAM design in nano-complementary metal oxide semiconductor technology

A write buffer design based on stable and area-saving embedded SRAM for flash applications

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems

An Area Efficient Built-In Redundancy Analysis for Embedded Memory with Selectable 1-D Redundancy

AN EFFECTIVE TEST ALGORITHM AND DIAGNOSTIC IMPLEMENTATION FOR EMBEDDED STATIC RANDOM ACCESS MEMORIES

Implications of Halo Implant Shadowing and Backscattering from Mask Layer Edges on Device Leakage Current in 65nm SRAM

A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme

Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs

Reduction of Area per Good Die for SoC Memory Built-In Self-Test

GuardiaNN: Fast and Secure On-Device Inference in TrustZone Using Embedded SRAM and Cryptographic Hardware

Area Efficient ROM-Embedded SRAM Cache

Power Characterization of Embedded SRAMs for Power Binning

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