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Data Conversion Handbook

Kester, Walt

1, 2004

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The science of plant‐based foods: Constructing next‐generation meat, fish, milk, and egg analogs

Comprehensive reviews in food science and food safety, 2021-07, Vol.20 (4), p.4049-4100

2021

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Erratum: “A Search for Analogs of KIC 8462852 (Boyajian’s Star): A Proof of Concept and the First Candidates” (2019, ApJL, 880, L7)

Astrophysical journal. Letters, 2020-09, Vol.900 (2), p.L46

Schmidt, Edward G.

2020

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Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

IEEE access, 2020-01, Vol.8, p.1-1

2020

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A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

IEEE journal of solid-state circuits, 2020-02, Vol.55 (2), p.312-321

2020

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Analog and Hybrid Computer Programming

Ulmann, Bernd

2, 2020

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Understanding Delta-Sigma Data Converters

Second Edition., 2017

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A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.6-18

2020

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IEEE_Xplore

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS

IEEE journal of solid-state circuits, 2019-09, Vol.54 (9), p.2532-2542

2019

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IEEE_Xplore

A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS

IEEE journal of solid-state circuits, 2018-01, Vol.53 (1), p.275-296

2018

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IEEE_Xplore

A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors

IEEE transactions on circuits and systems. I, Regular papers, 2020-12, Vol.67 (12), p.4396-4408

2020

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IEEE_Xplore

RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-02, Vol.40 (2), p.326-338

2021

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IEEE_Xplore

All-Digital High Resolution D/A Conversion by Dyadic Digital Pulse Modulation

IEEE transactions on circuits and systems. I, Regular papers, 2017-03, Vol.64 (3), p.573-584

Crovetti, Paolo S.

2017

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IEEE_Xplore

A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

IEEE journal of solid-state circuits, 2019-06, Vol.54 (6), p.1648-1656

2019

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IEEE_Xplore

1-bit Massive MU-MIMO Precoding in VLSI

IEEE journal on emerging and selected topics in circuits and systems, 2017-12, Vol.7 (4), p.508-522

2017

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IEEE_Xplore

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

IEEE journal of solid-state circuits, 2020-06, Vol.55 (6), p.1553-1564

2020

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IEEE_Xplore

A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1446-1454

2019

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IEEE_Xplore

A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter

IEEE journal of solid-state circuits, 2019-03, Vol.54 (3), p.636-645

Harpe, Pieter

2019

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IEEE_Xplore

Highly Digital Second-Order [Formula Omitted] VCO ADC

IEEE transactions on circuits and systems. I, Regular papers, 2019-07, Vol.66 (7), p.2415

2019

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Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

IEEE transactions on circuits and systems. I, Regular papers, 2022-06, Vol.69 (6), p.2249-2262

2022

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IEEE_Xplore

A Flexible Millimeter-Wave Channel Sounder With Absolute Timing

IEEE journal on selected areas in communications, 2017-06, Vol.35 (6), p.1402-1418

2017

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Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration

IEEE journal on emerging and selected topics in circuits and systems, 2019-06, Vol.9 (2), p.367-376

2019

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IEEE_Xplore

Ultra-Low Power SAR ADC Using Statistical Characteristics of Low-Activity Signals

IEEE transactions on very large scale integration (VLSI) systems, 2022-09, Vol.30 (9), p.1319-1331

2022

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IEEE_Xplore

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

IEEE journal of solid-state circuits, 2018-12, Vol.53 (12), p.3672-3687

2018

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An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS

IEEE transactions on very large scale integration (VLSI) systems, 2017-12, Vol.25 (12), p.3434-3443

2017

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IEEE_Xplore

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Data Conversion Handbook

The science of plant‐based foods: Constructing next‐generation meat, fish, milk, and egg analogs

Erratum: “A Search for Analogs of KIC 8462852 (Boyajian’s Star): A Proof of Concept and the First Candidates” (2019, ApJL, 880, L7)

Fully Synthesizable Low-Area Analogue-to-Digital Converters with Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

Analog and Hybrid Computer Programming

Understanding Delta-Sigma Data Converters

A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS

A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS

A High Area-Efficiency 14-bit SAR ADC With Hybrid Capacitor DAC for Array Sensors

RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars

All-Digital High Resolution D/A Conversion by Dyadic Digital Pulse Modulation

A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator

1-bit Massive MU-MIMO Precoding in VLSI

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC

A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter

Highly Digital Second-Order [Formula Omitted] VCO ADC

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

A Flexible Millimeter-Wave Channel Sounder With Absolute Timing

Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration

Ultra-Low Power SAR ADC Using Statistical Characteristics of Low-Activity Signals

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS

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