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2D Materials‐Based Static Random‐Access Memory

Advanced materials (Weinheim), 2022-12, Vol.34 (48), p.e2107894-n/a

2022

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Effects of TID on SRAM Data Retention Stability at the 5-nm Node

IEEE transactions on nuclear science, 2024-08, Vol.71 (8), p.1864-1871

2024

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Design and Stability analysis of CNTFET based SRAM cell

IOP conference series. Materials Science and Engineering, 2021-01, Vol.1033 (1), p.12043

2021

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A 4 V Operation, Flexible Braille Display Using Organic Transistors, Carbon Nanotube Actuators, and Organic Static Random-Access Memory

Advanced functional materials, 2011-11, Vol.21 (21), p.4019-4027

2011

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Fusion Neutron-Induced Soft Errors During Long Pulse D-D Plasma Discharges in the WEST Tokamak

IEEE transactions on nuclear science, 2024-08, Vol.71 (8), p.1496-1502

2024

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Characterization of Single-Event Upsets Induced by High LET Heavy Ions in 16 nm bulk FinFET SRAMs

IEEE transactions on nuclear science, 2022-05, Vol.69 (5), p.1-1

2022

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Voltage Dependence of Single-Event Cross-sections of FinFET SRAMs for Low LET Condition

IEEE transactions on nuclear science, 2023-08, Vol.70 (8), p.1-1

2023

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A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.146-151

2006

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Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices

IEEE transactions on circuits and systems. I, Regular papers, 2021-05, Vol.68 (5), p.1773-1786

2021

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A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks

IEEE journal of solid-state circuits, 2022-11, Vol.57 (11), p.3466-3476

2022

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One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

IEEE transactions on circuits and systems. I, Regular papers, 2020-05, Vol.67 (5), p.1551-1561

2020

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Design of low leakage process tolerant SRAM cell

Analog integrated circuits and signal processing, 2017-12, Vol.93 (3), p.531-538

2017

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A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1037-1050

2023

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CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

IEEE journal of solid-state circuits, 2021-06, Vol.56 (6), p.1924-1935

2021

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In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security

IEEE journal of solid-state circuits, 2022-01, Vol.57 (1), p.153-166

2022

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Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing

IEEE journal of solid-state circuits, 2021-08, Vol.56 (8), p.2550-2562

2021

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A New Design Paradigm for Auto-Nonvolatile Ternary SRAMs Using Ferroelectric CNTFETs: From Device to Array Architecture

IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.1-8

2022

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Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1087-1093

2023

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Non-volatile SRAM memory cells based on ReRAM technology

SN applied sciences, 2020-09, Vol.2 (9), p.1485, Article 1485

2020

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We-Quatro: Radiation-Hardened SRAM Cell With Parametric Process Variation Tolerance

IEEE transactions on nuclear science, 2017-09, Vol.64 (9), p.2489-2496

2017

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A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

IEEE transactions on circuits and systems. I, Regular papers, 2022-04, Vol.69 (4), p.1606-1616

2022

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A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations

IEEE journal of solid-state circuits, 2024-06, Vol.59 (6), p.1926-1937

2024

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In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations

IEEE journal of solid-state circuits, 2023-05, Vol.58 (5), p.1472-1486

2023

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A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

IEEE journal of solid-state circuits, 2024-01, Vol.59 (1), p.196-207

2024

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A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs

IEEE journal of solid-state circuits, 2024-09, Vol.59 (9), p.3032-3044

2024

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2D Materials‐Based Static Random‐Access Memory

Effects of TID on SRAM Data Retention Stability at the 5-nm Node

Design and Stability analysis of CNTFET based SRAM cell

A 4 V Operation, Flexible Braille Display Using Organic Transistors, Carbon Nanotube Actuators, and Organic Static Random-Access Memory

Fusion Neutron-Induced Soft Errors During Long Pulse D-D Plasma Discharges in the WEST Tokamak

Characterization of Single-Event Upsets Induced by High LET Heavy Ions in 16 nm bulk FinFET SRAMs

Voltage Dependence of Single-Event Cross-sections of FinFET SRAMs for Low LET Condition

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices

A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation

Design of low leakage process tolerant SRAM cell

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference

CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference

In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security

Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing

A New Design Paradigm for Auto-Nonvolatile Ternary SRAMs Using Ferroelectric CNTFETs: From Device to Array Architecture

Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology

Non-volatile SRAM memory cells based on ReRAM technology

We-Quatro: Radiation-Hardened SRAM Cell With Parametric Process Variation Tolerance

A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins

A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips

A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs

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