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"Zeppelin": An SoC for Multichip Architectures

IEEE journal of solid-state circuits, 2019-01, Vol.54 (1), p.133-143

2019

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Agile SoC Development with Open ESP : Invited Paper

2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020, p.1-9

2020

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DiaSys: Improving SoC insight through on-chip diagnosis

Journal of systems architecture, 2017-04, Vol.75, p.120-132

2017

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An FPGA-Based Embedded Robust Speech Recognition System Designed by Combining Empirical Mode Decomposition and a Genetic Algorithm

IEEE transactions on instrumentation and measurement, 2012-09, Vol.61 (9), p.2560-2572

2012

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DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip

Architecture of Computing Systems – ARCS 2016, p.197-209

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Towards spatial isolation design in a multi-core real-time kernel targeting safety-critical applications

International journal of critical computer-based systems, 2013, Vol.4 (3), p.248

2013

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Interacting Self-Timed Pipelines and Elementary Coupling Control Modules

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2009, Vol.E92-A (7), p.1642-1651

2009

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System on Chip (SOC) Architecture

System on Chip (SOC) Architecture, 2023, p.37-48

2023

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A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip

IEEE transactions on computer-aided design of integrated circuits and systems, 2005-04, Vol.24 (4), p.635-645

2005

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Design of Infant Gait Monitoring System Based on FPGA

2022 International Conference on Artificial Intelligence and Computer Information Technology (AICIT), 2022, p.1-4

2022

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An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2006-06, Vol.E89-A (6), p.1736-1739

LEE, S.

2006

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Introduction to Systems

System on Chip (SOC) Architecture, 2023, p.1-15

2023

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Optimal regulation of traffic flows in networks-on-chip

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010, p.1621-1624

2010

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A SoC-ZYNQ-Based SW-HW Co-Simulation and Verification Method

2019 Panhellenic Conference on Electronics & Telecommunications (PACET), 2019, p.1-6

2019

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Interpolated FFT Harmonic Analyzer for Power Systems, and System on a Chip (SOC) for It

SoutheastCon 2018, 2018, p.1-6

Jain, Vijay K.

2018

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Toolchain-based approach to handling variability in embedded multiprocessor system on chips

Chronic diseases and translational medicine, 2015-01, Vol.9 (1), p.82-92

2015

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From Bit Level Systolic Arrays to HDTV Processor Chips

Journal of signal processing systems, 2008-11, Vol.53 (1-2), p.35-49

2008

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Distributed architecture of touch screen controller SoC for large touch screen panels

2014 International SoC Design Conference (ISOCC), 2014, p.22-23

2014

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Work-in-progress: SSS: self-aware system-on-chip using static-dynamic hybrid method

2017 International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES), 2017, p.1-2

2017

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Internet Firewalls in the DECOS System-on-a-Chip Architecture

2007 5th IEEE International Conference on Industrial Informatics, 2007, Vol.2, p.983-988

2007

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Use-case based early performance simulation of cryptographic coprocessor

2013 International SoC Design Conference (ISOCC), 2013, p.056-059

2013

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LIN validation frame-work: a novel approach

2014 IEEE International Conference on Vehicular Electronics and Safety, 2014, p.163-167

2014

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Microcells for ICA-SOC for remote sensing of high energy radiation

2014 27th IEEE International System-on-Chip Conference (SOCC), 2014, p.119-124

Jain, Vijay K.

2014

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A hierarchical and parallel SoC architecture for vision procesor

IEICE Electronics Express, 2009-01, Vol.6 (19), p.1380-1386

2009

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Toward Bug-free Multicore SoC Architectures: System Validation with Transaction-Level Models

IEEE design & test of computers, 2011-05, Vol.28 (3), p.4-4

Anon., Anon

2011

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"Zeppelin": An SoC for Multichip Architectures

Agile SoC Development with Open ESP : Invited Paper

DiaSys: Improving SoC insight through on-chip diagnosis

An FPGA-Based Embedded Robust Speech Recognition System Designed by Combining Empirical Mode Decomposition and a Genetic Algorithm

DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip

Towards spatial isolation design in a multi-core real-time kernel targeting safety-critical applications

Interacting Self-Timed Pipelines and Elementary Coupling Control Modules

System on Chip (SOC) Architecture

A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip

Design of Infant Gait Monitoring System Based on FPGA

An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

Introduction to Systems

Optimal regulation of traffic flows in networks-on-chip

A SoC-ZYNQ-Based SW-HW Co-Simulation and Verification Method

Interpolated FFT Harmonic Analyzer for Power Systems, and System on a Chip (SOC) for It

Toolchain-based approach to handling variability in embedded multiprocessor system on chips

From Bit Level Systolic Arrays to HDTV Processor Chips

Distributed architecture of touch screen controller SoC for large touch screen panels

Work-in-progress: SSS: self-aware system-on-chip using static-dynamic hybrid method

Internet Firewalls in the DECOS System-on-a-Chip Architecture

Use-case based early performance simulation of cryptographic coprocessor

LIN validation frame-work: a novel approach

Microcells for ICA-SOC for remote sensing of high energy radiation

A hierarchical and parallel SoC architecture for vision procesor

Toward Bug-free Multicore SoC Architectures: System Validation with Transaction-Level Models

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