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Securing SoCs With FPGAs Against Rowhammer Attacks

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-07, Vol.41 (7), p.2052-2065

2022

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A Check-and-Balance Scheme in Multiphase Delay-Locked Loop

IEEE transactions on very large scale integration (VLSI) systems, 2024-07, Vol.32 (7), p.1253-1262

2024

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Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, Vol.32 (6), p.1124-1135

2024

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Impact of Particle Radiation and Temperature on the Retention Time of DDR4 SDRAM Cells

IEEE transactions on nuclear science, 2023-08, Vol.70 (8), p.1-1

2023

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Technology Dependence of Stuck Bits and Single Event Upsets in 110, 72, and 63-nm SDRAMs

IEEE transactions on nuclear science, 2023-08, Vol.70 (8), p.1-1

2023

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Constraint Models of SDRAM Based Arbitrary Waveform Generator

IEEE transactions on instrumentation and measurement, 2023-01, Vol.72, p.1-1

2023

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23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.378-380

2019

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DRAM Refresh Mechanisms, Penalties, and Trade-Offs

IEEE transactions on computers, 2016-01, Vol.65 (1), p.108-121

2016

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NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

IEEE computer architecture letters, 2015-07, Vol.14 (2), p.140-143

2015

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Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM

IEEE transactions on nuclear science, 2017-02, Vol.64 (2), p.859-866

2017

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An Algorithmic Approach to Observed Single Event Effects in Van Allen Probes Solid State Recorders

IEEE transactions on nuclear science, 2019-12, Vol.66 (12), p.2408-2416

2019

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Unaligned Burst-Aware Memory Subsystem

IEEE transactions on very large scale integration (VLSI) systems, 2019-10, Vol.27 (10), p.2387-2400

Jang, Wooyoung

2019

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Continuous-Flow Matrix Transposition Using Memories

IEEE transactions on circuits and systems. I, Regular papers, 2020-09, Vol.67 (9), p.3035-3046

2020

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A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

IEEE journal of solid-state circuits, 2024-10, Vol.59 (10), p.3479-3487

2024

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A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

IEEE journal of solid-state circuits, 2013-01, Vol.48 (1), p.168-177

2013

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A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA

Ain Shams Engineering Journal, 2024-03, Vol.15 (3), p.102478, Article 102478

2024

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Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3× nm technology

Microelectronics and reliability, 2016-02, Vol.57, p.39-46

2016

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Exploitations of Multiple Rows Hammering and Retention Time Interactions in DRAM Using X-Ray Radiation

IEEE access, 2021, Vol.9, p.137514-137523

2021

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Memory controller optimization for high-speed operation

AIP Conference Proceedings, 2023, Vol.2523 (1)

2023

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A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

IEEE transactions on circuits and systems. II, Express briefs, 2017-10, Vol.64 (10), p.1207-1211

2017

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A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.167-177

2020

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An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

IEEE journal of solid-state circuits, 2021-01, Vol.56 (1), p.212-224

2021

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A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.157-166

2020

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A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

IEEE journal of solid-state circuits, 2015-01, Vol.50 (1), p.178-190

2015

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Refresh Now and Then

IEEE transactions on computers, 2014-12, Vol.63 (12), p.3114-3126

2014

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Securing SoCs With FPGAs Against Rowhammer Attacks

A Check-and-Balance Scheme in Multiphase Delay-Locked Loop

Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices

Impact of Particle Radiation and Temperature on the Retention Time of DDR4 SDRAM Cells

Technology Dependence of Stuck Bits and Single Event Upsets in 110, 72, and 63-nm SDRAMs

Constraint Models of SDRAM Based Arbitrary Waveform Generator

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

DRAM Refresh Mechanisms, Penalties, and Trade-Offs

NVMain 2.0: A User-Friendly Memory Simulator to Model (Non-)Volatile Memory Systems

Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM

An Algorithmic Approach to Observed Single Event Effects in Van Allen Probes Solid State Recorders

Unaligned Burst-Aware Memory Subsystem

Continuous-Flow Matrix Transposition Using Memories

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

A novel algorithmic Data-Collision SDRAM-based TCAM architecture on FPGA

Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3× nm technology

Exploitations of Multiple Rows Hammering and Retention Time Interactions in DRAM Using X-Ray Radiation

Memory controller optimization for high-speed operation

A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Refresh Now and Then

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