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A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR

IEEE journal of solid-state circuits, 2024-02, Vol.59 (2), p.1-15

2024

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An Improved Algorithm for Q-scale Analysis in Jitter Decomposition

IEEE transactions on nuclear science, 2024-10, p.1-1

2024

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Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2024-07, Vol.71 (7), p.3157-3164

2024

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A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

IEEE journal of solid-state circuits, 2016-02, Vol.51 (2), p.428-439

2016

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The Accuracy of the Gaussian Tail and Dual Dirac Model in Jitter Histogram and Probability Density Functions

IEEE transactions on electromagnetic compatibility, 2022-12, Vol.64 (6), p.2207-2217

Soliman, George

2022

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Jitter Decomposition by Convolutional Neural Networks

IEEE transactions on electromagnetic compatibility, 2021-10, Vol.63 (5), p.1550-1561

2021

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Satellite Jitter Estimation and Validation Using Parallax Images

Sensors (Basel, Switzerland), 2017-01, Vol.17 (1), p.83-83

2017

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A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3253-3263

2009

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Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

IEEE transactions on very large scale integration (VLSI) systems, 2019-10, Vol.27 (10), p.2223-2236

2019

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A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

IEEE journal of solid-state circuits, 2019-05, Vol.54 (5), p.1407-1424

2019

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Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits

IEEE transactions on circuits and systems. I, Regular papers, 2013-06, Vol.60 (6), p.1381-1394

2013

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Information Rates With Non Ideal Photon Detectors in Time-Entanglement Based QKD

IEEE transactions on communications, 2023-04, Vol.71 (4), p.2246-2259

2023

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Performance Bounds of ADC-Based Receivers Due to Clock Jitter

IEEE transactions on circuits and systems. II, Express briefs, 2023-05, Vol.70 (5), p.1749-1753

2023

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Estimation and Analysis of NavIC Receiver Tracking Jitter due to Amplitude and Phase Scintillations

E3S web of conferences, 2024, Vol.540, p.14002

2024

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Simple Method for the Real-time Estimation of Timing Jitter in Ultrashort Pulses from Mode-locked Ultralong Ring Fiber Lasers

Journal of lightwave technology, 2024-09, p.1-5

2024

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Jitter-Power Trade-Offs in PLLs

IEEE transactions on circuits and systems. I, Regular papers, 2021-04, Vol.68 (4), p.1381-1387

Razavi, Behzad

2021

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Dual Phase-Locked Loop Design for Wireless Stable Radio Frequency Transmission

IEEE communications letters, 2024-11, p.1-1

2024

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A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

IEEE journal of solid-state circuits, 2017-11, Vol.52 (11), p.2963-2978

2017

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A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2021-01, Vol.68 (1), p.89-102

2021

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Jitter Detection and Image Restoration Based on Continue Dynamic Shooting Model for High-Resolution TDI CCD Satellite Images

IEEE transactions on geoscience and remote sensing, 2021-06, Vol.59 (6), p.4915-4933

2021

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Low-Power Built-in Jitter Injection Using Linearized Phase Interpolator

IEEE transactions on instrumentation and measurement, 2020-09, Vol.69 (9), p.6112-6120

2020

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Improved Jitter Distribution Tail-Fitting Algorithm for Decomposition of Random and Deterministic Jitter

IEEE transactions on electromagnetic compatibility, 2020-10, Vol.62 (5), p.1852-1858

Soliman, George

2020

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Relative Analysis of Channel Fading Models in Wireless Networks

International journal of innovative technology and exploring engineering, 2019-08, Vol.8 (9S3), p.871-874

2019

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A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.546-561

2022

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High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

IEEE transactions on circuits and systems. I, Regular papers, 2021-02, Vol.68 (2), p.741-750

2021

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A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR

An Improved Algorithm for Q-scale Analysis in Jitter Decomposition

Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

The Accuracy of the Gaussian Tail and Dual Dirac Model in Jitter Histogram and Probability Density Functions

Jitter Decomposition by Convolutional Neural Networks

Satellite Jitter Estimation and Validation Using Parallax Images

A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N

Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

Pseudo-Linear Analysis of Bang-Bang Controlled Timing Circuits

Information Rates With Non Ideal Photon Detectors in Time-Entanglement Based QKD

Performance Bounds of ADC-Based Receivers Due to Clock Jitter

Estimation and Analysis of NavIC Receiver Tracking Jitter due to Amplitude and Phase Scintillations

Simple Method for the Real-time Estimation of Timing Jitter in Ultrashort Pulses from Mode-locked Ultralong Ring Fiber Lasers

Jitter-Power Trade-Offs in PLLs

Dual Phase-Locked Loop Design for Wireless Stable Radio Frequency Transmission

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS

Jitter Detection and Image Restoration Based on Continue Dynamic Shooting Model for High-Resolution TDI CCD Satellite Images

Low-Power Built-in Jitter Injection Using Linearized Phase Interpolator

Improved Jitter Distribution Tail-Fitting Algorithm for Decomposition of Random and Deterministic Jitter

Relative Analysis of Channel Fading Models in Wireless Networks

A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

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