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A 0.007 mm2 48 - 53 GHz Low-Noise LC-Oscillator using an Ultra-Compact High-Q Resonator

2022 14th German Microwave Conference (GeMiC), 2022, p.104-107

2022

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0.012 mm2 800 µW 0.1–6.4 GHz multi-protocol PLL with 14 psrms integrated jitter in 28 nm FD-SOI

Electronics letters, 2016-09, Vol.52 (18), p.1518-1520

2016

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A 0.065-mm2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB

IEEE journal of solid-state circuits, 2017-07, Vol.52 (7), p.1927-1939

2017

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A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, p.165-168

2016

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0.075 × 0.075 mm2 ultra-small 7.5 μm ultra-thin RFID-chip mounting technology

2008 58th Electronic Components and Technology Conference, 2008, p.366-370

2008

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0.1 dB/cm waveguide losses in single-mode SOI rib waveguides

IEEE photonics technology letters, 1996-05, Vol.8 (5), p.647-648

1996

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A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

International journal of circuit theory and applications, 2018-04, Vol.46 (4), p.827-841

2018

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A 0.13 /spl mu/m full metal embedded DRAM technology targeting on 1.2 V, 450 MHz operation

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001, p.18.4.1-18.4.4

2001

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A 0.13 /spl mu/m high-performance SOI logic technology with embedded DRAM for system-on-a-chip application

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001, p.22.3.1-22.3.4

2001

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A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184), 2001, p.29-30

2001

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0.18 dB Low-Noise Figure at 10 GHz for GaN MIS-HEMT With Plasma-Enhanced Atomic Layer Deposition SiN Layer

IEEE electron device letters, 2023-07, Vol.44 (7), p.1080-1083

2023

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A 0.18/spl mu/m CMOS direct-conversion receiver front-end for UMTS

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002, Vol.2, p.192-468

2002

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0.18-μm fully-depleted silicon-on-insulator MOSFET's

IEEE electron device letters, 1997-06, Vol.18 (6), p.251-253

1997

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A 0.2-11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOS

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, p.335-338

2016

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A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999, p.438-439

1999

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A 0.2-/spl mu/m, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1430-1435

1999

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A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1436-1445

1999

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A 0.25 /spl mu/m 600 MHz 1.5 V SOI 64 b ALPHA/sup TM/ microprocessor

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), 1999, p.432-433

1999

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0.25 /spl mu/m merged bulk DRAM and SOI logic using patterned SOI

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104), 2000, p.66-67

2000

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0.25V FDSOI CMOS technology for ultra-low voltage applications

2002 IEEE International SOI Conference, 2002, p.37-38

2002

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A 0.2V-1.2V converter for power harvesting applications

ESSCIRC 2008 - 34th European Solid-State Circuits Conference, 2008, p.406-409

2008

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0.35 dB loss 20 dB coupling directional coupler integrated in 130 nm CMOS SOI technology targeting 3G PA SOC

2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in Rf Systems, 2014, p.29-31

2014

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A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment

IEEE transactions on microwave theory and techniques, 2022-04, Vol.70 (4), p.2236-2245

2022

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A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, p.433-436

2016

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A 0.38 V Fully Differential K-Band LNA with Transformer-Based Matching Networks

Applied sciences, 2023-04, Vol.13 (9), p.5460

2023

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1 – 25 von 72.483

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A 0.007 mm2 48 - 53 GHz Low-Noise LC-Oscillator using an Ultra-Compact High-Q Resonator

0.012 mm2 800 µW 0.1–6.4 GHz multi-protocol PLL with 14 psrms integrated jitter in 28 nm FD-SOI

A 0.065-mm2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB

A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB

0.075 × 0.075 mm2 ultra-small 7.5 μm ultra-thin RFID-chip mounting technology

0.1 dB/cm waveguide losses in single-mode SOI rib waveguides

A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

A 0.13 /spl mu/m full metal embedded DRAM technology targeting on 1.2 V, 450 MHz operation

A 0.13 /spl mu/m high-performance SOI logic technology with embedded DRAM for system-on-a-chip application

A 0.15 /spl mu/m logic based embedded DRAM technology featuring 0.425 /spl mu/m/sup 2/ stacked cell using MIM (metal-insulator-metal) capacitor

0.18 dB Low-Noise Figure at 10 GHz for GaN MIS-HEMT With Plasma-Enhanced Atomic Layer Deposition SiN Layer

A 0.18/spl mu/m CMOS direct-conversion receiver front-end for UMTS

0.18-μm fully-depleted silicon-on-insulator MOSFET's

A 0.2-11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOS

A 0.2 /spl mu/m 1.8 V SOI 550 MHz 64 b PowerPC microprocesser with copper interconnects

A 0.2-/spl mu/m, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects

A 0.25-/spl mu/m, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor

A 0.25 /spl mu/m 600 MHz 1.5 V SOI 64 b ALPHA/sup TM/ microprocessor

0.25 /spl mu/m merged bulk DRAM and SOI logic using patterned SOI

0.25V FDSOI CMOS technology for ultra-low voltage applications

A 0.2V-1.2V converter for power harvesting applications

0.35 dB loss 20 dB coupling directional coupler integrated in 130 nm CMOS SOI technology targeting 3G PA SOC

A 0.35-mW 70-GHz Self-Resonant E-TSPC Frequency Divider With Backgate Adjustment

A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI

A 0.38 V Fully Differential K-Band LNA with Transformer-Based Matching Networks

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