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HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-07, Vol.42 (7), p.1-1

2023

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Complexity Analysis of the SAT Attack on Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-10, Vol.42 (10), p.1-1

2023

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Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends

Computers & security, 2023-06, Vol.129, p.103196, Article 103196

2023

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On Improving the Security of Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2016-09, Vol.35 (9), p.1411-1424

2016

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Fault Analysis-Based Logic Encryption

IEEE transactions on computers, 2015-02, Vol.64 (2), p.410-424

2015

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HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

IEEE transactions on computer-aided design of integrated circuits and systems, 2009-10, Vol.28 (10), p.1493-1502

2009

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TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs

IEEE transactions on computers, 2023-08, Vol.72 (8), p.2306-2320

2023

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Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-12, Vol.39 (12), p.4439-4452

2020

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Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-02, Vol.37 (2), p.273-285

2018

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SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-05, Vol.42 (5), p.1406-1410

2023

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LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-04, Vol.41 (4), p.854-867

2022

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GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking

IEEE transactions on very large scale integration (VLSI) systems, 2024-02, Vol.32 (2), p.361-371

2024

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Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2023-04, Vol.42 (4), p.1044-1057

2023

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Security analysis of integrated circuit camouflaging

Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security, 2013, p.709-720

2013

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An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies

IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2456-2469

2018

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LOTUS: A Scalable Framework to Lock Multi-Module Designs With One-Time Key and Self-Destructive Approaches

IEEE embedded systems letters, 2024, p.1-1

2024

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ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-10, Vol.41 (10), p.3202-3215

2022

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Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs

Computers & electrical engineering, 2023-10, Vol.111, p.108928, Article 108928

2023

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TAAL: Tampering Attack on Any Key-based Logic Locked Circuits

ACM transactions on design automation of electronic systems, 2021-04, Vol.26 (4), p.1-22

2021

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Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy

Computer (Long Beach, Calif.), 2017-05, Vol.50 (5), p.62-71

2017

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Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework

IEEE access, 2024, Vol.12, p.47494-47507

2024

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Trace Logic Locking: Improving the Parametric Space of Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2021-08, Vol.40 (8), p.1531-1544

2021

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Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis

Microprocessors and microsystems, 2023-10, Vol.102, p.104916, Article 104916

2023

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Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging

IEEE transactions on information forensics and security, 2017-11, Vol.12 (11), p.2668-2682

2017

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ATPG-based cost-effective, secure logic locking

2018 IEEE 36th VLSI Test Symposium (VTS), 2018, p.1-6

2018

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HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language

Complexity Analysis of the SAT Attack on Logic Locking

Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends

On Improving the Security of Logic Locking

Fault Analysis-Based Logic Encryption

HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs

Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective

Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation

SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation

LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection

GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking

Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis

Security analysis of integrated circuit camouflaging

An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies

LOTUS: A Scalable Framework to Lock Multi-Module Designs With One-Time Key and Self-Destructive Approaches

ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment

Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs

TAAL: Tampering Attack on Any Key-based Logic Locked Circuits

Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy

Watermarking Hardware IPs Using Design Parameter Driven Encrypted Dispersion Matrix With Eigen Decomposition Based Security Framework

Trace Logic Locking: Improving the Parametric Space of Logic Locking

Exploration of optimal crypto-chain signature embedded secure JPEG-CODEC hardware IP during high level synthesis

Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging

ATPG-based cost-effective, secure logic locking

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