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Functional Design-for-Testability for Functional Test Sequences

IEEE transactions on computer-aided design of integrated circuits and systems, 2024, p.1-1

Pomeranz, Irith

2024

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SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan

ACM transactions on design automation of electronic systems, 2024-09

Pomeranz, Irith

2024

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Built-In Self-Test of SFQ Circuits Using Side-Channel Leakage Information

IEEE transactions on very large scale integration (VLSI) systems, 2024-06, Vol.32 (6), p.1100-1109

2024

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A Comprehensive Comparison Between Design for Testability Techniques for Total Dose Testing of Flash-Based FPGAs

IEEE transactions on nuclear science, 2021-08, Vol.68 (8), p.2232-2238

2021

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Functional Compaction for Functional Test Sequences

IEEE access, 2024, Vol.12, p.98130-98140

Pomeranz, Irith

2024

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Parallel-Series Multiobjective Genetic Algorithm for Optimal Tests Selection With Multiple Constraints

IEEE transactions on instrumentation and measurement, 2018-08, Vol.67 (8), p.1859-1876

Yang, Chenglin

2018

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Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-12, Vol.38 (12), p.2357-2365

Pomeranz, Irith

2019

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Oscillation-Based Prebond TSV Test

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-09, Vol.32 (9), p.1440-1444

2013

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Logic operation-based Design for Testability method and parallel test algorithm for 1T1R crossbar

Electronics letters, 2017-12, Vol.53 (25), p.1631-1632

2017

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Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT

2022 IEEE International Test Conference (ITC), 2022, p.400-409

2022

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Time-Multiplexed 1687-Network for Test Cost Reduction

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-08, Vol.37 (8), p.1681-1691

2018

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Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing

IEEE transactions on semiconductor manufacturing, 2020-08, Vol.33 (3), p.391-403

2020

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Measuring and improving software testability at the design level

Information and software technology, 2024-10, Vol.174, p.107511, Article 107511

2024

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Secured Flipped Scan-Chain Model for Crypto-Architecture

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-11, Vol.26 (11), p.2080-2084

2007

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Selective decoration of nitrogenated holey graphene (C2N) with titanium clusters for enhanced hydrogen storage application

International journal of hydrogen energy, 2021-02, Vol.46 (10), p.7371-7380

2021

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Can experiment determine the stacking fault energy of metastable alloys?

Materials & design, 2021-02, Vol.199, p.109396, Article 109396

2021

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A Fully Integrated BIST \Delta \Sigma ADC Using the In-Phase and Quadrature Waves Fitting Procedure

IEEE transactions on instrumentation and measurement, 2014-12, Vol.63 (12), p.2750-2760

2014

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Multidimensional Fitness Function DPSO Algorithm for Analog Test Point Selection

IEEE transactions on instrumentation and measurement, 2010-06, Vol.59 (6), p.1634-1641

2010

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Testing of quantum cellular automata

IEEE transactions on nanotechnology, 2004-12, Vol.3 (4), p.432-442

2004

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Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking

IEEE transactions on computer-aided design of integrated circuits and systems, 2015-06, Vol.34 (6), p.961-971

2015

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DefScan: Provably Defeating Scan Attack on AES-Like Ciphers

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-08, Vol.43 (8), p.2326-2339

2024

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Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption

IEEE transactions on computer-aided design of integrated circuits and systems, 2019-03, Vol.38 (3), p.538-550

2019

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Testability Evaluation for Local Design Modifications

IEEE transactions on very large scale integration (VLSI) systems, 2024-01, Vol.32 (1), p.195-199

Pomeranz, Irith

2024

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Single Flux Quantum Integrated Circuit Design

1, 2021

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Efficient Test Compression Configuration Selection

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-07, Vol.41 (7), p.2323-2336

2022

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Functional Design-for-Testability for Functional Test Sequences

SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan

Built-In Self-Test of SFQ Circuits Using Side-Channel Leakage Information

A Comprehensive Comparison Between Design for Testability Techniques for Total Dose Testing of Flash-Based FPGAs

Functional Compaction for Functional Test Sequences

Parallel-Series Multiobjective Genetic Algorithm for Optimal Tests Selection With Multiple Constraints

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences

Oscillation-Based Prebond TSV Test

Logic operation-based Design for Testability method and parallel test algorithm for 1T1R crossbar

Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT

Time-Multiplexed 1687-Network for Test Cost Reduction

Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing

Measuring and improving software testability at the design level

Secured Flipped Scan-Chain Model for Crypto-Architecture

Selective decoration of nitrogenated holey graphene (C2N) with titanium clusters for enhanced hydrogen storage application

Can experiment determine the stacking fault energy of metastable alloys?

A Fully Integrated BIST \Delta \Sigma ADC Using the In-Phase and Quadrature Waves Fitting Procedure

Multidimensional Fitness Function DPSO Algorithm for Analog Test Point Selection

Testing of quantum cellular automata

Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking

DefScan: Provably Defeating Scan Attack on AES-Like Ciphers

Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption

Testability Evaluation for Local Design Modifications

Single Flux Quantum Integrated Circuit Design

Efficient Test Compression Configuration Selection

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