UB Paderborn / Katalog / Suche / in CDI

Efficient Monolithic SAW Convolver Using Poly(3-Hexylthiophene)

IEEE transactions on instrumentation and measurement, 2023, Vol.72, p.1-7

2023

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IEEE_Xplore

High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-5

2020

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IEEE_Xplore

deconvolveR : A G-Modeling Program for Deconvolution and Empirical Bayes Estimation

Journal of statistical software, 2020, Vol.94 (11), p.1-20

2020

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Design and Application of an Approximate 2-D Convolver with Error Compensation

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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AI-assisted on-chip nanophotonic convolver based on silicon metasurface

Nanophotonics (Berlin, Germany), 2020-09, Vol.9 (10), p.3315-3322

2020

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Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

IEEE transactions on circuits and systems. II, Express briefs, 2016-10, Vol.63 (10), p.979-983

2016

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IEEE_Xplore

Performance-Aware Architectures for Parallel 4D Color fMRI Filtering Algorithm: A Complete Performance Indices Package

IEEE transactions on parallel and distributed systems, 2016-07, Vol.27 (7), p.2116-2129

Hasan, Sami

2016

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IEEE_Xplore

A Fine-Grained Pipelined 2-D Convolver for High-Performance Applications

IEEE transactions on circuits and systems. II, Express briefs, 2019-01, Vol.66 (1), p.146-150

2019

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IEEE_Xplore

Real-time approximate and combined 2D convolvers for FPGA-based image processing

The Journal of supercomputing, 2023-11, Vol.79 (16), p.18910-18946

2023

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Enhanced Efficiency 3D Convolution Based on Optimal FPGA Accelerator

IEEE access, 2017, Vol.5, p.6909-6916

2017

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NeuFlow: A runtime reconfigurable dataflow processor for vision

CVPR 2011 WORKSHOPS, 2011, p.109-116

2011

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IEEE_Xplore

Design and analysis of an approximate 2D convolver

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2016, p.31-34

2016

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IEEE_Xplore

Robust and Large-Scale Convolution through Stochastic-Based Processing without Multipliers

IEEE transactions on emerging topics in computing, 2019-01, Vol.7 (1), p.80-97

2019

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IEEE_Xplore

Binary convolutional neural network on RRAM

2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 2017, p.782-787

2017

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IEEE_Xplore

Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2006-02, Vol.53 (2), p.105-109

2006

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IEEE_Xplore

Real time acoustic convolution of RF signals using organic semiconductor

2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2024, p.1-3

2024

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A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2007-02, Vol.54 (2), p.200-204

2007

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IEEE_Xplore

Multirate-Based Fast Parallel Algorithms for 2-D DHT-Based Real-Valued Discrete Gabor Transform

IEEE transactions on image processing, 2012-07, Vol.21 (7), p.3306-3311

2012

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IEEE_Xplore

Multirate-based fast parallel algorithms for DCT-kernel-based real-valued discrete Gabor transform

Signal processing, 2012-03, Vol.92 (3), p.679-684

2012

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A convolver-based real-time stereo machine (SAZAN)

Proceedings - IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 1999, Vol.1, p.457-463 Vol. 1

1999

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IEEE_Xplore

Reconfigurable pipelined 2-D convolvers for fast digital signal processing

IEEE transactions on very large scale integration (VLSI) systems, 1999-09, Vol.7 (3), p.299-308

1999

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IEEE_Xplore

FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations

Advances in electrical and computer engineering, 2015-01, Vol.15 (1), p.95-104

2015

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Automatic code generation of convolutional neural networks in FPGA implementation

2016 International Conference on Field-Programmable Technology (FPT), 2016, p.61-68

2016

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Fast hard multiple generators for radix-8 Booth encoded modulo 2n−1 and modulo 2n+1 multipliers

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.717-720

2010

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IEEE_Xplore

A power and area efficient architecture of convolver based on ram

2009 IEEE 8th International Conference on ASIC, 2009, p.835-838

2009

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IEEE_Xplore

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Einstellungen

Efficient Monolithic SAW Convolver Using Poly(3-Hexylthiophene)

High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme

deconvolveR : A G-Modeling Program for Deconvolution and Empirical Bayes Estimation

Design and Application of an Approximate 2-D Convolver with Error Compensation

AI-assisted on-chip nanophotonic convolver based on silicon metasurface

Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing

Performance-Aware Architectures for Parallel 4D Color fMRI Filtering Algorithm: A Complete Performance Indices Package

A Fine-Grained Pipelined 2-D Convolver for High-Performance Applications

Real-time approximate and combined 2D convolvers for FPGA-based image processing

Enhanced Efficiency 3D Convolution Based on Optimal FPGA Accelerator

NeuFlow: A runtime reconfigurable dataflow processor for vision

Design and analysis of an approximate 2D convolver

Robust and Large-Scale Convolution through Stochastic-Based Processing without Multipliers

Binary convolutional neural network on RRAM

Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing

Real time acoustic convolution of RF signals using organic semiconductor

A Multiwindow Partial Buffering Scheme for FPGA-Based 2-D Convolvers

Multirate-Based Fast Parallel Algorithms for 2-D DHT-Based Real-Valued Discrete Gabor Transform

Multirate-based fast parallel algorithms for DCT-kernel-based real-valued discrete Gabor transform

A convolver-based real-time stereo machine (SAZAN)

Reconfigurable pipelined 2-D convolvers for fast digital signal processing

FPGA Based Compact and Efficient Full Image Buffering for Neighborhood Operations

Automatic code generation of convolutional neural networks in FPGA implementation

Fast hard multiple generators for radix-8 Booth encoded modulo 2n−1 and modulo 2n+1 multipliers

A power and area efficient architecture of convolver based on ram

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