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Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

IEEE journal of solid-state circuits, 2008-07, Vol.43 (7), p.1699-1710

2008

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Gate diffusion input based 4-bit Vedic multiplier design

IET circuits, devices & systems, 2018-11, Vol.12 (6), p.764-770

2018

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Ultralow-Power Design in Near-Threshold Region

Proceedings of the IEEE, 2010-02, Vol.98 (2), p.237-252

2010

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High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits

IEEE transactions on magnetics, 2009-10, Vol.45 (10), p.3784-3787

2009

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Air-stable N-type printed carbon nanotube thin film transistors for CMOS logic circuits

Carbon (New York), 2020-08, Vol.163, p.145-153

2020

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Measuring the Gap Between FPGAs and ASICs

IEEE transactions on computer-aided design of integrated circuits and systems, 2007-02, Vol.26 (2), p.203-215

2007

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Demonstration of Single-Flux-Quantum 64-B Lookup Table With Cryo-CMOS Decoders for Reconfiguration

IEEE transactions on applied superconductivity, 2022-11, Vol.32 (8), p.1-5

2022

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An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs

IEEE transactions on circuits and systems. I, Regular papers, 2017-08, Vol.64 (8), p.2026-2035

2017

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A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations

IEEE journal of solid-state circuits, 2008-01, Vol.43 (1), p.69-77

2008

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Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

IEEE transactions on circuits and systems. I, Regular papers, 2010-07, Vol.57 (7), p.1597-1607

Alioto, Massimo

2010

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Charge Collection and Charge Sharing in a 130 nm CMOS Technology

IEEE transactions on nuclear science, 2006-12, Vol.53 (6), p.3253-3258

2006

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Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device

IEEE electron device letters, 2009-02, Vol.30 (2), p.158-160

2009

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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

IEEE journal of solid-state circuits, 2010-01, Vol.45 (1), p.111-119

2010

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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

IEEE transactions on very large scale integration (VLSI) systems, 2006-12, Vol.14 (12), p.1309-1321

2006

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Static noise margin variation for sub-threshold SRAM in 65-nm CMOS

IEEE journal of solid-state circuits, 2006-07, Vol.41 (7), p.1673-1679

2006

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A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

IET computers & digital techniques, 2013-07, Vol.7 (4), p.167-181

2013

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High-performance and single event double-upset-immune latch design

Electronics letters, 2020-11, Vol.56 (23), p.1243-1245

2020

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Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

IEEE transactions on nuclear science, 2009-12, Vol.56 (6), p.3050-3056

2009

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Power‐jitter trade‐off analysis in digital‐to‐time converters

Electronics letters, 2017-03, Vol.53 (5), p.306-308

2017

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A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

IEEE journal of solid-state circuits, 2008-02, Vol.43 (2), p.518-529

2008

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An effective nano design of demultiplexer architecture based on coplanar quantum‐dot cellular automata

IET circuits, devices & systems, 2021-03, Vol.15 (2), p.168-174

2021

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Challenges to adopting adiabatic circuits for systems‐on‐a‐chip

IET circuits, devices & systems, 2021-09, Vol.15 (6), p.581-593

2021

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Differential Electrically Insulated Magnetoelectric Spin-Orbit Logic Circuits

IEEE journal on exploratory solid-state computational devices and circuits, 2021-06, Vol.7 (1), p.18-25

2021

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Leakage current: Moore's law meets static power

Computer (Long Beach, Calif.), 2003-12, Vol.36 (12), p.68-75

2003

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Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2004-10, Vol.51 (10), p.1985-1997

2004

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Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

Gate diffusion input based 4-bit Vedic multiplier design

Ultralow-Power Design in Near-Threshold Region

High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits

Air-stable N-type printed carbon nanotube thin film transistors for CMOS logic circuits

Measuring the Gap Between FPGAs and ASICs

Demonstration of Single-Flux-Quantum 64-B Lookup Table With Cryo-CMOS Decoders for Reconfiguration

An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs

A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations

Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis

Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Bilayer PseudoSpin Field-Effect Transistor (BiSFET): A Proposed New Logic Device

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

Static noise margin variation for sub-threshold SRAM in 65-nm CMOS

A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits

High-performance and single event double-upset-immune latch design

Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

Power‐jitter trade‐off analysis in digital‐to‐time converters

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

An effective nano design of demultiplexer architecture based on coplanar quantum‐dot cellular automata

Challenges to adopting adiabatic circuits for systems‐on‐a‐chip

Differential Electrically Insulated Magnetoelectric Spin-Orbit Logic Circuits

Leakage current: Moore's law meets static power

Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits

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