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Area-delay eﬀicient Radix-4 8×8 Booth multiplier for DSP applications

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES, 2021-07, Vol.29 (4), p.2012-2028

2021

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A high speed pipelined radix-16 Booth multiplier architecture for FPGA implementation

International journal of electronics and communications, 2024-10, Vol.185, p.155435, Article 155435

2024

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AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators

IEEE transactions on circuits and systems. II, Express briefs, 2021-05, Vol.68 (5), p.1566-1570

2021

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A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing

IEEE transactions on circuits and systems. I, Regular papers, 2020-12, Vol.67 (12), p.4794-4803

2020

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Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications

IEEE transactions on nanotechnology, 2022, Vol.21, p.81-89

2022

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Design of Approximate Radix-256 Booth Encoding for Error-Tolerant Computing

IEEE transactions on circuits and systems. II, Express briefs, 2022-04, Vol.69 (4), p.2286-2290

2022

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A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation

IEEE transactions on circuits and systems. II, Express briefs, 2018-02, Vol.65 (2), p.236-240

2018

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A low-cost high-speed radix-4 Montgomery modular multiplier without carry-propagate format conversion

Engineering science and technology, an international journal, 2024-06, Vol.54, p.101703, Article 101703

2024

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Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors

IEEE transactions on very large scale integration (VLSI) systems, 2023-09, Vol.31 (9), p.1-9

2023

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Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application

Integration (Amsterdam), 2024-09, Vol.98, p.102215, Article 102215

2024

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A Modified Partial Product Generator for Redundant Binary Multipliers

IEEE transactions on computers, 2016-04, Vol.65 (4), p.1165-1171

2016

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On the design of logarithmic multiplier using Radix-4 Booth encoding

IEEE access, 2020-01, Vol.8, p.1-1

2020

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Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding

IEEE journal on emerging and selected topics in circuits and systems, 2023-03, Vol.13 (1), p.165-174

Mohanty, Basant Kumar

2023

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A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier

IEEE transactions on computers, 2016-11, Vol.65 (11), p.3251-3264

2016

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Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

IEEE open journal of circuits and systems, 2020, Vol.1, p.76-87

2020

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Performance comparison review of Radix-based multiplier designs

2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012), 2012, Vol.2, p.854-859

2012

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A Novel DA-Based Parallel Architecture for Inner-Product of Variable Vectors

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array

Electronics (Basel), 2024-01, Vol.13 (2), p.311

2024

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Improved Signed Binary Multiplier Through New Partial Product Generation Scheme

Journal of circuits, systems, and computers, 2021-07, Vol.30 (9), p.2150162

2021

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FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

Applied sciences, 2023-09, Vol.13 (18), p.10407

2023

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Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers

IEEE transactions on computers, 2011-02, Vol.60 (2), p.148-156

2011

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Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies

Electronics (Basel), 2023-05, Vol.12 (10), p.2177

2023

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Circuit Level Realization of Low Latency Radix-4 Booth Scheme for Parallel Multipliers

National Academy of Sciences, India. Proceedings. Section A. Physical Sciences, 2022, Vol.92 (2), p.293-301

2022

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Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier

Advances in electrical and electronic engineering, 2021-09, Vol.19 (3), p.272-281

2021

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Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

IEEE transactions on computers, 2016-02, Vol.65 (2), p.670-676

2016

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Area-delay eﬀicient Radix-4 8×8 Booth multiplier for DSP applications

A high speed pipelined radix-16 Booth multiplier architecture for FPGA implementation

AxBMs: Approximate Radix-8 Booth Multipliers for High-Performance FPGA-Based Accelerators

A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing

Design of Majority Logic-Based Approximate Booth Multipliers for Error-Tolerant Applications

Design of Approximate Radix-256 Booth Encoding for Error-Tolerant Computing

A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation

A low-cost high-speed radix-4 Montgomery modular multiplier without carry-propagate format conversion

Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors

Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application

A Modified Partial Product Generator for Redundant Binary Multipliers

On the design of logarithmic multiplier using Radix-4 Booth encoding

Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding

A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier

Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders

Performance comparison review of Radix-based multiplier designs

A Novel DA-Based Parallel Architecture for Inner-Product of Variable Vectors

Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array

Improved Signed Binary Multiplier Through New Partial Product Generation Scheme

FPGA Implementation of a Novel Multifunction Modulo (2n ± 1) Multiplier Using Radix-4 Booth Encoding Scheme

Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers

Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies

Circuit Level Realization of Low Latency Radix-4 Booth Scheme for Parallel Multipliers

Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding

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