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Analysis and Design of a 60 GHz Wideband Voltage-Voltage Transformer Feedback LNA

IEEE transactions on microwave theory and techniques, 2012-03, Vol.60 (3), p.702-713

2012

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A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

IEEE transactions on very large scale integration (VLSI) systems, 2015-01, Vol.23 (1), p.44-53

2015

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A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems

IEEE journal of solid-state circuits, 2010-09, Vol.45 (9), p.1697-1709

2010

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A Low-Voltage Chopper-Stabilized Amplifier for Fetal ECG Monitoring With a 1.41 Power Efficiency Factor

IEEE transactions on biomedical circuits and systems, 2015-04, Vol.9 (2), p.237-247

2015

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A 30/35 GHz Dual-Band Transmitter for Phased Arrays in Communication/Radar Applications

IEEE journal of solid-state circuits, 2015-07, Vol.50 (7), p.1629-1644

2015

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Adaptive Impedance-Matching Techniques for Controlling L Networks

IEEE transactions on circuits and systems. I, Regular papers, 2010-02, Vol.57 (2), p.495-505

2010

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A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver

IEEE journal of solid-state circuits, 2019-02, Vol.54 (2), p.417-427

2019

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Synthesis‐oriented double‐loop feedback model

International journal of circuit theory and applications, 2017-12, Vol.45 (12), p.1901-1919

2017

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An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

IEEE transactions on circuits and systems. I, Regular papers, 2012-05, Vol.59 (5), p.906-914

2012

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A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz

IEEE journal of solid-state circuits, 2016-06, Vol.51 (6), p.1374-1384

2016

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Front End Power Dissipation Minimization and Optimal Transmission Rate for Wireless Receivers

IEEE transactions on circuits and systems. I, Regular papers, 2014-05, Vol.61 (5), p.1566-1577

2014

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A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

IEEE journal of solid-state circuits, 2011-06, Vol.46 (6), p.1371-1381

2011

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A Noise Reconfigurable Current-Reuse Resistive Feedback Amplifier With Signal-Dependent Power Consumption for Fetal ECG Monitoring

IEEE sensors journal, 2016-12, Vol.16 (23), p.8304-8313

2016

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System Level Receiver Design for Minimum Sensitivity to Process Variations

IEEE transactions on circuits and systems. I, Regular papers, 2011-10, Vol.58 (10), p.2296-2307

2011

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A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz

IEEE transactions on very large scale integration (VLSI) systems, 2015-09, Vol.23 (9), p.1941-1945

2015

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A GSM/EDGE/WCDMA Adaptive Series-LC Matching Network Using RF-MEMS Switches

IEEE journal of solid-state circuits, 2008-10, Vol.43 (10), p.2259-2268

2008

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Analogue Frontend Amplifiers for Bio-Potential Measurements Manufactured With a-IGZO TFTs on Flexible Substrate

IEEE journal on emerging and selected topics in circuits and systems, 2017-03, Vol.7 (1), p.60-70

2017

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Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2007-02, Vol.54 (2), p.146-150

2007

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A Background Calibration Technique Based on Limit Cycles for Reconfigurable Sigma Delta Modulators

IEEE journal on emerging and selected topics in circuits and systems, 2015-12, Vol.5 (4), p.584-597

2015

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A 1 mA Ultra-Low-Power FHSS TX Front-End Utilizing Direct Modulation With Digital Pre-Distortion

IEEE journal of solid-state circuits, 2007-10, Vol.42 (10), p.2212-2223

2007

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A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free "Swap To Reset"

IEEE journal of solid-state circuits, 2017-11, Vol.52 (11), p.2979-2990

2017

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Bitstream switching rate based calibration of delta-sigma modulators

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.2293-2296

2015

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A low-voltage folded-switching mixer in 0.18-μm CMOS

IEEE journal of solid-state circuits, 2005-06, Vol.40 (6), p.1259-1264

2005

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Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer

IEEE journal of solid-state circuits, 2006-03, Vol.41 (3), p.588-596

2006

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A 0.20 \text ^2 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS

IEEE journal of solid-state circuits, 2016-01, Vol.51 (1), p.240-248

2016

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Analysis and Design of a 60 GHz Wideband Voltage-Voltage Transformer Feedback LNA

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme

A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems

A Low-Voltage Chopper-Stabilized Amplifier for Fetal ECG Monitoring With a 1.41 Power Efficiency Factor

A 30/35 GHz Dual-Band Transmitter for Phased Arrays in Communication/Radar Applications

Adaptive Impedance-Matching Techniques for Controlling L Networks

A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver

Synthesis‐oriented double‐loop feedback model

An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals

A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz

Front End Power Dissipation Minimization and Optimal Transmission Rate for Wireless Receivers

A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 < -83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping

A Noise Reconfigurable Current-Reuse Resistive Feedback Amplifier With Signal-Dependent Power Consumption for Fetal ECG Monitoring

System Level Receiver Design for Minimum Sensitivity to Process Variations

A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz

A GSM/EDGE/WCDMA Adaptive Series-LC Matching Network Using RF-MEMS Switches

Analogue Frontend Amplifiers for Bio-Potential Measurements Manufactured With a-IGZO TFTs on Flexible Substrate

Brownian-Bridge-Based Statistical Analysis of the DAC INL Caused by Current Mismatch

A Background Calibration Technique Based on Limit Cycles for Reconfigurable Sigma Delta Modulators

A 1 mA Ultra-Low-Power FHSS TX Front-End Utilizing Direct Modulation With Digital Pre-Distortion

A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free "Swap To Reset"

Bitstream switching rate based calibration of delta-sigma modulators

A low-voltage folded-switching mixer in 0.18-μm CMOS

Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer

A 0.20 \text ^2 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS

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