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Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

IEEE access, 2020, Vol.8, p.75809-75821

2020

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Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography

IEEE access, 2020, Vol.8, p.163419-163433

2020

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A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

Journal of low power electronics and applications, 2019, Vol.9 (1), p.9

2019

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Cost-effective fixed-point hardware support for RISC-V embedded systems

Journal of systems architecture, 2022-05, Vol.126, p.102476, Article 102476

2022

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Efficient and Scalable FPGA Design of GF( 2^m2m) Inversion for Post-Quantum Cryptosystems

IEEE transactions on computers, 2022-12, Vol.71 (12), p.3295-3307

2022

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A Survey on Run-time Power Monitors at the Edge

ACM computing surveys, 2023-07, Vol.55 (14s), p.1-33, Article 325

2023

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Design of Side-Channel-Resistant Power Monitors

IEEE transactions on computer-aided design of integrated circuits and systems, 2022-05, Vol.41 (5), p.1249-1263

2022

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Design-time methodology for optimizing mixed-precision CPU architectures on FPGA

Journal of systems architecture, 2024-10, Vol.155, p.103257, Article 103257

2024

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Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks

IEEE transactions on computer-aided design of integrated circuits and systems, 2020-09, Vol.39 (9), p.1778-1791

2020

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All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores

IEEE transactions on computers, 2020-05, Vol.69 (5), p.706-721

2020

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An FPU design template to optimize the accuracy-efficiency-area trade-off

Sustainable computing informatics and systems, 2021-03, Vol.29, p.100450, Article 100450

2021

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Automatic identification and hardware implementation of a resource-constrained power model for embedded systems

Sustainable computing informatics and systems, 2021-03, Vol.29, p.100467, Article 100467

2021

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CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs

IEEE transactions on parallel and distributed systems, 2016-06, Vol.27 (6), p.1603-1616

2016

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DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks

ACM transactions on architecture and code optimization, 2018-06, Vol.15 (2), p.1-26

2018

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A Deep- Learning Technique to Locate Cryptographic Operations in Side-Channel Traces

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, p.1-6

2024

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A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture

ACM transactions on design automation of electronic systems, 2018-10, Vol.23 (5), p.1-30

2018

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All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs

IEEE embedded systems letters, 2020-03, Vol.12 (1), p.17-20

2020

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Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators

Journal of systems architecture, 2022-07, Vol.128, p.102553, Article 102553

2022

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Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

ACM journal on emerging technologies in computing systems, 2015-09, Vol.12 (3), p.1-24

2015

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BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

Journal of parallel and distributed computing, 2017-06, Vol.104, p.130-145

2017

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PowerTap: All-digital power meter modeling for run-time power monitoring

Microprocessors and microsystems, 2018-11, Vol.63, p.128-139

2018

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PowerProbe: Run-time power modeling through automatic RTL instrumentation

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, p.743-748

2018

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Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems

2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2023, p.1-6

2023

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A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

Journal of signal processing systems, 2016-06, Vol.83 (3), p.357-371

2016

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FPGA implementation of BIKE for quantum-resistant TLS

2022 25th Euromicro Conference on Digital System Design (DSD), 2022, p.539-547

2022

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Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography

A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era

Cost-effective fixed-point hardware support for RISC-V embedded systems

Efficient and Scalable FPGA Design of GF( 2^m2m) Inversion for Post-Quantum Cryptosystems

A Survey on Run-time Power Monitors at the Edge

Design of Side-Channel-Resistant Power Monitors

Design-time methodology for optimizing mixed-precision CPU architectures on FPGA

Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks

All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores

An FPU design template to optimize the accuracy-efficiency-area trade-off

Automatic identification and hardware implementation of a resource-constrained power model for embedded systems

CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs

DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks

A Deep- Learning Technique to Locate Cryptographic Operations in Side-Channel Traces

A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture

All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs

Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators

Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers

PowerTap: All-digital power meter modeling for run-time power monitoring

PowerProbe: Run-time power modeling through automatic RTL instrumentation

Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems

A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations

FPGA implementation of BIKE for quantum-resistant TLS

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