UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Real-Time Multi-Chip Neural Network for Cognitive Systems

1, 2018

Volltextzugriff (PDF)

Brain-Machine Interface: Circuits and Systems

Zjajo, Amir

1, 2016

Volltextzugriff (PDF)

Power-Efficiency of Signal Processing Circuits in Implantable Multichannel Brain-Machine Interface

Journal of low-power electronics, 2016-12, Vol.12 (4), p.342-351

Zjajo, Amir

2016

Volltextzugriff (PDF)

Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors

IEEE transactions on very large scale integration (VLSI) systems, 2017-04, Vol.25 (4), p.1549-1562

2017

Volltextzugriff (PDF)

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters

Journal of low-power electronics, 2012-04, Vol.8 (2), p.182-196

2012

Volltextzugriff (PDF)

Immediate Neighborhood Temperature Adaptive Routing for Dynamically Throttled 3-D Networks-on-Chip

IEEE transactions on circuits and systems. II, Express briefs, 2017-07, Vol.64 (7), p.782-786

2017

Volltextzugriff (PDF)

Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC

IEEE transactions on very large scale integration (VLSI) systems, 2014-09, Vol.22 (9), p.1920-1933

2014

Volltextzugriff (PDF)

A 41 μW real-time adaptive neural spike classifier

2016 IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI), 2016, p.489-492

2016

Volltextzugriff (PDF)

A 2.1 μW/channel current-mode integrated neural recording interface

2016 IEEE-EMBS International Conference on Biomedical and Health Informatics (BHI), 2016, p.505-508

2016

Volltextzugriff (PDF)

A sub-nW neuromorphic receptors for wide-range temporal patterns of post-synaptic responses in 65 nm CMOS

Analog integrated circuits and signal processing, 2019-03, Vol.98 (3), p.477-488

2019

Volltextzugriff (PDF)

A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation

IEEE transactions on biomedical circuits and systems, 2018-04, Vol.12 (2), p.326-337

2018

Volltextzugriff (PDF)

Dynamic Homeostatic Regulation in Energy-Efficient Time-Locked Neuromorphic Systems

2020 IEEE 20th International Conference on Bioinformatics and Bioengineering (BIBE), 2020, p.719-722

Zjajo, Amir

2020

Volltextzugriff (PDF)

System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

IEEE transactions on very large scale integration (VLSI) systems, 2014-07, Vol.22 (7), p.1606-1619

2014

Volltextzugriff (PDF)

Considering Crosstalk Effects in Statistical Timing Analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-02, Vol.33 (2), p.318-322

2014

Volltextzugriff (PDF)

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver

IEEE transactions on computer-aided design of integrated circuits and systems, 2014-02, Vol.33 (2), p.210-223

2014

Volltextzugriff (PDF)

Neurosynaptic Computational Elements for Adaptive Transient Synchrony: Biophysical Accuracy versus Hardware Complexity

2019 IEEE 11th International Workshop on Computational Intelligence and Applications (IWCIA), 2019, p.3-8

Zjajo, Amir

2019

Volltextzugriff (PDF)

Stochastic noise analysis of neural interface front end

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.169-172

2015

Volltextzugriff (PDF)

Uncertainty in Noise-Driven Steady-State Neuromorphic Network for ECG Data Classification

2018 IEEE 31st International Symposium on Computer-Based Medical Systems (CBMS), 2018, p.434-435

2018

Volltextzugriff (PDF)

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

IEEE transactions on instrumentation and measurement, 2012-08, Vol.61 (8), p.2212-2221

2012

Volltextzugriff (PDF)

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs

IEEE transactions on circuits and systems. I, Regular papers, 2011-01, Vol.58 (1), p.164-175

2011

Volltextzugriff (PDF)

A low-power digitally-programmable variable gain amplifier in 65 nm CMOS

2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2010, p.105-110

2010

Volltextzugriff (PDF)

A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.85-88

2014

Volltextzugriff (PDF)

Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits

Journal of low-power electronics, 2013-12, Vol.9 (4), p.403-413

2013

Volltextzugriff (PDF)

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test

IEEE transactions on very large scale integration (VLSI) systems, 2009-10, Vol.17 (10), p.1383-1391

2009

Volltextzugriff (PDF)

ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus

Journal of electronic testing, 2012-08, Vol.28 (4), p.393-404

2012

Volltextzugriff (PDF)

1 – 25 von 110

Menü

Weitere Dienste

Einstellungen

Real-Time Multi-Chip Neural Network for Cognitive Systems

Brain-Machine Interface: Circuits and Systems

Power-Efficiency of Signal Processing Circuits in Implantable Multichannel Brain-Machine Interface

Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters

Immediate Neighborhood Temperature Adaptive Routing for Dynamically Throttled 3-D Networks-on-Chip

Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC

A 41 μW real-time adaptive neural spike classifier

A 2.1 μW/channel current-mode integrated neural recording interface

A sub-nW neuromorphic receptors for wide-range temporal patterns of post-synaptic responses in 65 nm CMOS

A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation

Dynamic Homeostatic Regulation in Energy-Efficient Time-Locked Neuromorphic Systems

System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs

Considering Crosstalk Effects in Statistical Timing Analysis

Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver

Neurosynaptic Computational Elements for Adaptive Transient Synchrony: Biophysical Accuracy versus Hardware Complexity

Stochastic noise analysis of neural interface front end

Uncertainty in Noise-Driven Steady-State Neuromorphic Network for ECG Data Classification

Low-Power Die-Level Process Variation and Temperature Monitors for Yield Analysis and Optimization in Deep-Submicron CMOS

Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs

A low-power digitally-programmable variable gain amplifier in 65 nm CMOS

A 0.1pJ Freeze Vernier time-to-digital converter in 65nm CMOS

Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits

Analog Automatic Test Pattern Generation for Quasi-Static Structural Test

ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus

Suchergebnisse filtern