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Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays

IEEE transactions on very large scale integration (VLSI) systems, 2008-02, Vol.16 (2), p.134-143

Zipf, P.

2008

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The XPP Architecture and Its Co-simulation Within the Simulink Environment

Field Programmable Logic and Application, 2004, p.761-770

2004

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Simulation von CNFET basierten Digitalschaltungen

Advances in radio science, 2006-01, Vol.4, p.307-311

2006

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Simulation von CNFET basierten Digitalschaltungen

Advances in radio science, 2006-09, Vol.4 (9), p.307-311

2006

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Pipelined adder graph optimization for high speed multiple constant multiplication

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.49-52

2012

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Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures

Field Programmable Logic and Application, 2003, p.1111-1114

2003

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A multichannel high-resolution (<5 ps RMS between two channels) Time-to-Digital Converter (TDC) implemented in a field programmable gate array (FPGA)

2011 IEEE Nuclear Science Symposium Conference Record, 2011, p.876-879

2011

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Functional modeling techniques for a wireless LAN OFDM transceiver

2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2005, p.3970-3973 Vol. 4

2005

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Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension

Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, 2002, p.586-595

2002

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A Framework for Teaching (Re)Configurable Architectures in Student Projects

Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, 2002, p.444-451

2002

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Fly — A Modifiable Hardware Compiler

Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, 2002, p.381-390

2002

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System Design with Genetic Algorithms

Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing, 2000, p.250-259

2000

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Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II

2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, 2008, p.196-202

2008

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IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter

Field Programmable Logic and Application, 2004, p.526-535

2004

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A switch architecture and signal synchronization for GALS system-on-chips

Proceedings of the 17th symposium on Integrated circuits and system design, 2004, p.210-215

2004

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A configurable pipelined state machine as a hybrid ASIC and configurable architecture

IEEE Computer Society Annual Symposium on VLSI, 2004, p.266-267

2004

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High speed low complexity FPGA-based FIR filters using pipelined adder graphs

2011 International Conference on Field-Programmable Technology, 2011, p.1-4

2011

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A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.6 pp.

2006

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CONAN - a design exploration framework for reliable nano-electronics architectures

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), 2005, p.260-267

2005

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UbiComp device for a decentralized distributed computing environment

Proceedings of the 3rd IEEE International Symposium on Signal Processing and Information Technology (IEEE Cat. No.03EX795), 2003, p.782-785

2003

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Hybrid multiple constant multiplication for FPGAs

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012), 2012, p.556-559

2012

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On a hardware architecture for the evolution of cellular automata functionality

International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005, 2005, Vol.1, p.91-94 Vol. 1

2005

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Reduced complexity single and multiple constant multiplication in floating point precision

22nd International Conference on Field Programmable Logic and Applications (FPL), 2012, p.255-261

2012

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Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system

22nd International Conference on Field Programmable Logic and Applications (FPL), 2012, p.591-594

2012

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Towards a unique FPGA-based identification circuit using process variations

2009 International Conference on Field Programmable Logic and Applications, 2009, p.397-402

2009

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Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays

The XPP Architecture and Its Co-simulation Within the Simulink Environment

Simulation von CNFET basierten Digitalschaltungen

Simulation von CNFET basierten Digitalschaltungen

Pipelined adder graph optimization for high speed multiple constant multiplication

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures

A multichannel high-resolution (<5 ps RMS between two channels) Time-to-Digital Converter (TDC) implemented in a field programmable gate array (FPGA)

Functional modeling techniques for a wireless LAN OFDM transceiver

Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension

A Framework for Teaching (Re)Configurable Architectures in Student Projects

Fly — A Modifiable Hardware Compiler

System Design with Genetic Algorithms

Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II

IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter

A switch architecture and signal synchronization for GALS system-on-chips

A configurable pipelined state machine as a hybrid ASIC and configurable architecture

High speed low complexity FPGA-based FIR filters using pipelined adder graphs

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

CONAN - a design exploration framework for reliable nano-electronics architectures

UbiComp device for a decentralized distributed computing environment

Hybrid multiple constant multiplication for FPGAs

On a hardware architecture for the evolution of cellular automata functionality

Reduced complexity single and multiple constant multiplication in floating point precision

Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system

Towards a unique FPGA-based identification circuit using process variations

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